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2 files changed

+180
-2
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‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2822,9 +2822,13 @@ SDValue SITargetLowering::LowerFormalArguments(
28222822
const Function &Fn = MF.getFunction();
28232823
FunctionType *FType = MF.getFunction().getFunctionType();
28242824
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2825+
bool IsUnsupportedHsa = false;
28252826

28262827
if (Subtarget->isAmdHsaOS() && AMDGPU::isGraphics(CallConv)) {
2827-
report_fatal_error("unsupported non-compute shaders with HSA");
2828+
DiagnosticInfoUnsupported NoGraphicsHSA(
2829+
Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
2830+
DAG.getContext()->diagnose(NoGraphicsHSA);
2831+
IsUnsupportedHsa = true;
28282832
}
28292833

28302834
SmallVector<ISD::InputArg, 16> Splits;
@@ -2933,7 +2937,7 @@ SDValue SITargetLowering::LowerFormalArguments(
29332937

29342938
for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
29352939
const ISD::InputArg &Arg = Ins[i];
2936-
if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
2940+
if ((Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) || IsUnsupportedHsa) {
29372941
InVals.push_back(DAG.getUNDEF(Arg.VT));
29382942
continue;
29392943
}

‎llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll‎

Lines changed: 174 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,174 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --tool not --version 5
2+
; RUN: not llc -mtriple=amdgcn-unknown-amdhsa -O0 -stop-after=amdgpu-isel -o - < %s 2>&1 | FileCheck %s
3+
4+
@I = global i32 42
5+
@P = global ptr @I
6+
7+
; CHECK: error: <unknown>:0:0: in function pixel_shader_zero_args void (): unsupported non-compute shaders with HSA
8+
; CHECK: error: <unknown>:0:0: in function pixel_shader_one_arg void (ptr): unsupported non-compute shaders with HSA
9+
; CHECK: error: <unknown>:0:0: in function pixel_shader_two_args void (ptr, i32): unsupported non-compute shaders with HSA
10+
; CHECK: error: <unknown>:0:0: in function vertex_shader_zero_args void (): unsupported non-compute shaders with HSA
11+
; CHECK: error: <unknown>:0:0: in function vertex_shader_one_arg void (ptr): unsupported non-compute shaders with HSA
12+
; CHECK: error: <unknown>:0:0: in function vertex_shader_two_args void (ptr, i32): unsupported non-compute shaders with HSA
13+
; CHECK: error: <unknown>:0:0: in function geometry_shader_zero_args void (): unsupported non-compute shaders with HSA
14+
; CHECK: error: <unknown>:0:0: in function geometry_shader_one_arg void (ptr): unsupported non-compute shaders with HSA
15+
; CHECK: error: <unknown>:0:0: in function geometry_shader_two_args void (ptr, i32): unsupported non-compute shaders with HSA
16+
17+
; CHECK-LABEL: name: pixel_shader_zero_args
18+
; CHECK: bb.0 (%ir-block.0):
19+
; CHECK-NEXT: %2:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
20+
; CHECK-NEXT: %3:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %2, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
21+
; CHECK-NEXT: %5:vreg_64 = COPY %3
22+
; CHECK-NEXT: %4:vgpr_32 = FLAT_LOAD_DWORD killed %5, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
23+
; CHECK-NEXT: %6:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @P, target-flags(amdgpu-gotprel32-hi) @P, implicit-def dead $scc
24+
; CHECK-NEXT: %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %6, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
25+
; CHECK-NEXT: %8:vreg_64 = COPY %7
26+
; CHECK-NEXT: FLAT_STORE_DWORD killed %8, killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into @P)
27+
; CHECK-NEXT: S_ENDPGM 0
28+
define amdgpu_ps void @pixel_shader_zero_args() {
29+
%i = load i32, ptr @I
30+
store i32 %i, ptr @P
31+
ret void
32+
}
33+
34+
; CHECK-LABEL: name: pixel_shader_one_arg
35+
; CHECK: bb.0 (%ir-block.0):
36+
; CHECK-NEXT: %4:sreg_32 = IMPLICIT_DEF
37+
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
38+
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
39+
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
40+
; CHECK-NEXT: %3:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, %6, %subreg.sub1
41+
; CHECK-NEXT: %2:vreg_64 = COPY %3
42+
; CHECK-NEXT: %8:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
43+
; CHECK-NEXT: %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %8, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
44+
; CHECK-NEXT: %11:vreg_64 = COPY %9
45+
; CHECK-NEXT: %10:vgpr_32 = FLAT_LOAD_DWORD killed %11, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
46+
; CHECK-NEXT: %12:vreg_64 = COPY %3
47+
; CHECK-NEXT: FLAT_STORE_DWORD %12, killed %10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.p)
48+
; CHECK-NEXT: S_ENDPGM 0
49+
define amdgpu_ps void @pixel_shader_one_arg(ptr %p) {
50+
%i = load i32, ptr @I
51+
store i32 %i, ptr %p
52+
ret void
53+
}
54+
55+
; CHECK-LABEL: name: pixel_shader_two_args
56+
; CHECK: bb.0 (%ir-block.0):
57+
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
58+
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
59+
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
60+
; CHECK-NEXT: %8:sreg_32 = IMPLICIT_DEF
61+
; CHECK-NEXT: %4:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %7, %subreg.sub1
62+
; CHECK-NEXT: %3:vgpr_32 = IMPLICIT_DEF
63+
; CHECK-NEXT: %2:vreg_64 = COPY %4
64+
; CHECK-NEXT: S_ENDPGM 0
65+
define amdgpu_ps void @pixel_shader_two_args(ptr %p, i32 %i) {
66+
store i32 %i, ptr %p
67+
ret void
68+
}
69+
70+
; CHECK-LABEL: name: vertex_shader_zero_args
71+
; CHECK: bb.0 (%ir-block.0):
72+
; CHECK-NEXT: %2:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
73+
; CHECK-NEXT: %3:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %2, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
74+
; CHECK-NEXT: %5:vreg_64 = COPY %3
75+
; CHECK-NEXT: %4:vgpr_32 = FLAT_LOAD_DWORD killed %5, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
76+
; CHECK-NEXT: %6:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @P, target-flags(amdgpu-gotprel32-hi) @P, implicit-def dead $scc
77+
; CHECK-NEXT: %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %6, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
78+
; CHECK-NEXT: %8:vreg_64 = COPY %7
79+
; CHECK-NEXT: FLAT_STORE_DWORD killed %8, killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into @P)
80+
; CHECK-NEXT: S_ENDPGM 0
81+
define amdgpu_vs void @vertex_shader_zero_args() {
82+
%i = load i32, ptr @I
83+
store i32 %i, ptr @P
84+
ret void
85+
}
86+
87+
; CHECK-LABEL: name: vertex_shader_one_arg
88+
; CHECK: bb.0 (%ir-block.0):
89+
; CHECK-NEXT: %4:sreg_32 = IMPLICIT_DEF
90+
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
91+
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
92+
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
93+
; CHECK-NEXT: %3:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, %6, %subreg.sub1
94+
; CHECK-NEXT: %2:vreg_64 = COPY %3
95+
; CHECK-NEXT: %8:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
96+
; CHECK-NEXT: %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %8, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
97+
; CHECK-NEXT: %11:vreg_64 = COPY %9
98+
; CHECK-NEXT: %10:vgpr_32 = FLAT_LOAD_DWORD killed %11, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
99+
; CHECK-NEXT: %12:vreg_64 = COPY %3
100+
; CHECK-NEXT: FLAT_STORE_DWORD %12, killed %10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.p)
101+
; CHECK-NEXT: S_ENDPGM 0
102+
define amdgpu_vs void @vertex_shader_one_arg(ptr %p) {
103+
%i = load i32, ptr @I
104+
store i32 %i, ptr %p
105+
ret void
106+
}
107+
108+
; CHECK-LABEL: name: vertex_shader_two_args
109+
; CHECK: bb.0 (%ir-block.0):
110+
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
111+
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
112+
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
113+
; CHECK-NEXT: %8:sreg_32 = IMPLICIT_DEF
114+
; CHECK-NEXT: %4:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %7, %subreg.sub1
115+
; CHECK-NEXT: %3:vgpr_32 = IMPLICIT_DEF
116+
; CHECK-NEXT: %2:vreg_64 = COPY %4
117+
; CHECK-NEXT: S_ENDPGM 0
118+
define amdgpu_vs void @vertex_shader_two_args(ptr %p, i32 %i) {
119+
store i32 %i, ptr %p
120+
ret void
121+
}
122+
123+
; CHECK-LABEL: name: geometry_shader_zero_args
124+
; CHECK: bb.0 (%ir-block.0):
125+
; CHECK-NEXT: %2:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
126+
; CHECK-NEXT: %3:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %2, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
127+
; CHECK-NEXT: %5:vreg_64 = COPY %3
128+
; CHECK-NEXT: %4:vgpr_32 = FLAT_LOAD_DWORD killed %5, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
129+
; CHECK-NEXT: %6:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @P, target-flags(amdgpu-gotprel32-hi) @P, implicit-def dead $scc
130+
; CHECK-NEXT: %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %6, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
131+
; CHECK-NEXT: %8:vreg_64 = COPY %7
132+
; CHECK-NEXT: FLAT_STORE_DWORD killed %8, killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into @P)
133+
; CHECK-NEXT: S_ENDPGM 0
134+
define amdgpu_gs void @geometry_shader_zero_args() {
135+
%i = load i32, ptr @I
136+
store i32 %i, ptr @P
137+
ret void
138+
}
139+
140+
; CHECK-LABEL: name: geometry_shader_one_arg
141+
; CHECK: bb.0 (%ir-block.0):
142+
; CHECK-NEXT: %4:sreg_32 = IMPLICIT_DEF
143+
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
144+
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
145+
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
146+
; CHECK-NEXT: %3:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, %6, %subreg.sub1
147+
; CHECK-NEXT: %2:vreg_64 = COPY %3
148+
; CHECK-NEXT: %8:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @I, target-flags(amdgpu-gotprel32-hi) @I, implicit-def dead $scc
149+
; CHECK-NEXT: %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %8, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
150+
; CHECK-NEXT: %11:vreg_64 = COPY %9
151+
; CHECK-NEXT: %10:vgpr_32 = FLAT_LOAD_DWORD killed %11, 0, 0, implicit $exec, implicit $flat_scr :: (dereferenceable load (s32) from @I)
152+
; CHECK-NEXT: %12:vreg_64 = COPY %3
153+
; CHECK-NEXT: FLAT_STORE_DWORD %12, killed %10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.p)
154+
; CHECK-NEXT: S_ENDPGM 0
155+
define amdgpu_gs void @geometry_shader_one_arg(ptr %p) {
156+
%i = load i32, ptr @I
157+
store i32 %i, ptr %p
158+
ret void
159+
}
160+
161+
; CHECK-LABEL: name: geometry_shader_two_args
162+
; CHECK: bb.0 (%ir-block.0):
163+
; CHECK-NEXT: %5:sreg_32 = IMPLICIT_DEF
164+
; CHECK-NEXT: %6:sreg_32 = IMPLICIT_DEF
165+
; CHECK-NEXT: %7:sreg_32 = IMPLICIT_DEF
166+
; CHECK-NEXT: %8:sreg_32 = IMPLICIT_DEF
167+
; CHECK-NEXT: %4:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %7, %subreg.sub1
168+
; CHECK-NEXT: %3:vgpr_32 = IMPLICIT_DEF
169+
; CHECK-NEXT: %2:vreg_64 = COPY %4
170+
; CHECK-NEXT: S_ENDPGM 0
171+
define amdgpu_gs void @geometry_shader_two_args(ptr %p, i32 %i) {
172+
store i32 %i, ptr %p
173+
ret void
174+
}

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