[X86] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::BLENDV nodes when upper elements are not demanded.

Prep work for #83402

Author: RKSimon

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -42521,6 +42521,8 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
     }
       // Zero upper elements.
     case X86ISD::VZEXT_MOVL:
+      // Variable blend.
+    case X86ISD::BLENDV:
       // Target unary shuffles by immediate:
     case X86ISD::PSHUFD:
     case X86ISD::PSHUFLW:

llvm/test/CodeGen/X86/vector-half-conversions.ll

@@ -5217,9 +5217,8 @@ define <4 x i32> @fptoui_4f16_to_4i32(<4 x half> %a) nounwind {
 ; F16C-NEXT:    vcvttps2dq %ymm0, %ymm1
 ; F16C-NEXT:    vsubps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
 ; F16C-NEXT:    vcvttps2dq %ymm0, %ymm0
-; F16C-NEXT:    vorps %ymm0, %ymm1, %ymm0
-; F16C-NEXT:    vblendvps %ymm1, %ymm0, %ymm1, %ymm0
-; F16C-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
+; F16C-NEXT:    vorps %xmm0, %xmm1, %xmm0
+; F16C-NEXT:    vblendvps %xmm1, %xmm0, %xmm1, %xmm0
 ; F16C-NEXT:    vzeroupper
 ; F16C-NEXT:    retq
 ;