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[Exegesis][RISCV] Support C_LDSP for llvm-exegesis (#169660)
Fix error: ``` *** Bad machine code: Illegal physical register for instruction *** - function: foo - basic block: %bb.0 (0x5e2262bd3f20) - instruction: $x10 = C_LDSP $x10, 0 - operand 1: $x10 $x10 is not a SP register. llvm-exegesis error: The machine function failed verification. ```
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llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s

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@@ -46,3 +46,12 @@ C_SRLI-NEXT: key:
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C_SRLI-NEXT: instructions:
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C_SRLI-NEXT: - 'C_SRLI [[REG101:X[0-9]+]] [[REG102:X[0-9]+]] [[IMM10:i_0x[0-9]+]]'
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C_SRLI-DAG: ...
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_LDSP -mattr=+c | FileCheck --check-prefix=C_LDSP %s
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C_LDSP: ---
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C_LDSP-NEXT: mode: latency
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C_LDSP-NEXT: key:
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C_LDSP-NEXT: instructions:
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C_LDSP-NEXT: - 'C_LDSP X2 X2 [[IMM11:i_0x[0-9]+]]'
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C_LDSP-DAG: ...

llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp

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@@ -819,6 +819,15 @@ void ExegesisRISCVTarget::fillMemoryOperands(InstructionTemplate &IT,
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assert(MemOp.isReg() && "Memory operand expected to be register");
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unsigned Opcode = I.getOpcode();
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if (Opcode == RISCV::C_LDSP || Opcode == RISCV::C_LWSP ||
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Opcode == RISCV::C_SDSP || Opcode == RISCV::C_SWSP) {
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IT.getValueFor(I.Operands[0]) = MCOperand::createReg(RISCV::X2);
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// Force base register to SP (X2)
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IT.getValueFor(MemOp) = MCOperand::createReg(RISCV::X2);
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return;
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}
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IT.getValueFor(MemOp) = MCOperand::createReg(Reg);
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}
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llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp

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@@ -142,7 +142,12 @@ static void appendCodeTemplates(const LLVMState &State,
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return;
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ET.fillMemoryOperands(Variant, ScratchMemoryRegister, 0);
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Variant.getValueFor(DefOp) = MCOperand::createReg(ScratchMemoryRegister);
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// Only force the def register to ScratchMemoryRegister if the target
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// hasn't assigned a value yet.
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MCOperand &DefVal = Variant.getValueFor(DefOp);
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if (!DefVal.isValid())
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DefVal = MCOperand::createReg(ScratchMemoryRegister);
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CodeTemplate CT;
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CT.Execution = ExecutionModeBit;

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