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[lldb][LoongArch] Complete register alias name in AugmentRegisterInfo
Fixes: #123903 Reviewed By: DavidSpickett, SixWeining Pull Request: #124059
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5 files changed

+138
-61
lines changed

5 files changed

+138
-61
lines changed

‎lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp‎

Lines changed: 17 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include <limits>
1313
#include <sstream>
1414

15+
#include "llvm/ADT/StringRef.h"
1516
#include "llvm/IR/DerivedTypes.h"
1617
#include "llvm/Support/MathExtras.h"
1718

@@ -644,34 +645,25 @@ void ABISysV_loongarch::AugmentRegisterInfo(
644645
std::vector<lldb_private::DynamicRegisterInfo::Register> &regs) {
645646
lldb_private::RegInfoBasedABI::AugmentRegisterInfo(regs);
646647

648+
static const llvm::StringMap<llvm::StringRef> isa_to_abi_alias_map = {
649+
{"r0", "zero"}, {"r1", "ra"}, {"r2", "tp"}, {"r3", "sp"},
650+
{"r4", "a0"}, {"r5", "a1"}, {"r6", "a2"}, {"r7", "a3"},
651+
{"r8", "a4"}, {"r9", "a5"}, {"r10", "a6"}, {"r11", "a7"},
652+
{"r12", "t0"}, {"r13", "t1"}, {"r14", "t2"}, {"r15", "t3"},
653+
{"r16", "t4"}, {"r17", "t5"}, {"r18", "t6"}, {"r19", "t7"},
654+
{"r20", "t8"}, {"r22", "fp"}, {"r23", "s0"}, {"r24", "s1"},
655+
{"r25", "s2"}, {"r26", "s3"}, {"r27", "s4"}, {"r28", "s5"},
656+
{"r29", "s6"}, {"r30", "s7"}, {"r31", "s8"}};
657+
647658
for (auto it : llvm::enumerate(regs)) {
659+
llvm::StringRef reg_name = it.value().name.GetStringRef();
660+
648661
// Set alt name for certain registers for convenience
649-
if (it.value().name == "r0")
650-
it.value().alt_name.SetCString("zero");
651-
else if (it.value().name == "r1")
652-
it.value().alt_name.SetCString("ra");
653-
else if (it.value().name == "r3")
654-
it.value().alt_name.SetCString("sp");
655-
else if (it.value().name == "r22")
656-
it.value().alt_name.SetCString("fp");
657-
else if (it.value().name == "r4")
658-
it.value().alt_name.SetCString("a0");
659-
else if (it.value().name == "r5")
660-
it.value().alt_name.SetCString("a1");
661-
else if (it.value().name == "r6")
662-
it.value().alt_name.SetCString("a2");
663-
else if (it.value().name == "r7")
664-
it.value().alt_name.SetCString("a3");
665-
else if (it.value().name == "r8")
666-
it.value().alt_name.SetCString("a4");
667-
else if (it.value().name == "r9")
668-
it.value().alt_name.SetCString("a5");
669-
else if (it.value().name == "r10")
670-
it.value().alt_name.SetCString("a6");
671-
else if (it.value().name == "r11")
672-
it.value().alt_name.SetCString("a7");
662+
llvm::StringRef alias_name = isa_to_abi_alias_map.lookup(reg_name);
663+
if (!alias_name.empty())
664+
it.value().alt_name.SetString(alias_name);
673665

674666
// Set generic regnum so lldb knows what the PC, etc is
675-
it.value().regnum_generic = GetGenericNum(it.value().name.GetStringRef());
667+
it.value().regnum_generic = GetGenericNum(reg_name);
676668
}
677669
}

‎lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py‎

Lines changed: 43 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -866,41 +866,42 @@ def test_loongarch64_regs(self):
866866
self.assertTrue(target, VALID_TARGET)
867867
process = target.LoadCore("linux-loongarch64.core")
868868

869-
values = {}
870-
values["r0"] = "0x0000000000000000"
871-
values["r1"] = "0x000000012000016c"
872-
values["r2"] = "0x0000000000000000"
873-
values["r3"] = "0x00007ffffb8249e0"
874-
values["r4"] = "0x0000000000000000"
875-
values["r5"] = "0x000000012000010c"
876-
values["r6"] = "0x0000000000000000"
877-
values["r7"] = "0x0000000000000000"
878-
values["r8"] = "0x0000000000000000"
879-
values["r9"] = "0x0000000000000000"
880-
values["r10"] = "0x0000000000000000"
881-
values["r11"] = "0x00000000000000dd"
882-
values["r12"] = "0x0000000000000000"
883-
values["r13"] = "0x000000000000002f"
884-
values["r14"] = "0x0000000000000000"
885-
values["r15"] = "0x0000000000000000"
886-
values["r16"] = "0x0000000000000000"
887-
values["r17"] = "0x0000000000000000"
888-
values["r18"] = "0x0000000000000000"
889-
values["r19"] = "0x0000000000000000"
890-
values["r20"] = "0x0000000000000000"
891-
values["r21"] = "0x0000000000000000"
892-
values["r22"] = "0x00007ffffb824a10"
893-
values["r23"] = "0x0000000000000000"
894-
values["r24"] = "0x0000000000000000"
895-
values["r25"] = "0x0000000000000000"
896-
values["r26"] = "0x0000000000000000"
897-
values["r27"] = "0x0000000000000000"
898-
values["r28"] = "0x0000000000000000"
899-
values["r29"] = "0x0000000000000000"
900-
values["r30"] = "0x0000000000000000"
901-
values["r31"] = "0x0000000000000000"
902-
values["orig_a0"] = "0x0000555556b62d50"
903-
values["pc"] = "0x000000012000012c"
869+
values = {
870+
"r0": ("0x0000000000000000", "zero"),
871+
"r1": ("0x000000012000016c", "ra"),
872+
"r2": ("0x0000000000000000", "tp"),
873+
"r3": ("0x00007ffffb8249e0", "sp"),
874+
"r4": ("0x0000000000000000", "a0"),
875+
"r5": ("0x000000012000010c", "a1"),
876+
"r6": ("0x0000000000000000", "a2"),
877+
"r7": ("0x0000000000000000", "a3"),
878+
"r8": ("0x0000000000000000", "a4"),
879+
"r9": ("0x0000000000000000", "a5"),
880+
"r10": ("0x0000000000000000", "a6"),
881+
"r11": ("0x00000000000000dd", "a7"),
882+
"r12": ("0x0000000000000000", "t0"),
883+
"r13": ("0x000000000000002f", "t1"),
884+
"r14": ("0x0000000000000000", "t2"),
885+
"r15": ("0x0000000000000000", "t3"),
886+
"r16": ("0x0000000000000000", "t4"),
887+
"r17": ("0x0000000000000000", "t5"),
888+
"r18": ("0x0000000000000000", "t6"),
889+
"r19": ("0x0000000000000000", "t7"),
890+
"r20": ("0x0000000000000000", "t8"),
891+
"r21": ("0x0000000000000000", None),
892+
"r22": ("0x00007ffffb824a10", "fp"),
893+
"r23": ("0x0000000000000000", "s0"),
894+
"r24": ("0x0000000000000000", "s1"),
895+
"r25": ("0x0000000000000000", "s2"),
896+
"r26": ("0x0000000000000000", "s3"),
897+
"r27": ("0x0000000000000000", "s4"),
898+
"r28": ("0x0000000000000000", "s5"),
899+
"r29": ("0x0000000000000000", "s6"),
900+
"r30": ("0x0000000000000000", "s7"),
901+
"r31": ("0x0000000000000000", "s8"),
902+
"orig_a0": ("0x0000555556b62d50", None),
903+
"pc": ("0x000000012000012c", None),
904+
}
904905

905906
fpr_values = {}
906907
fpr_values["f0"] = "0x00000000ffffff05"
@@ -945,11 +946,17 @@ def test_loongarch64_regs(self):
945946
fpr_values["fcc7"] = "0x01"
946947
fpr_values["fcsr"] = "0x00000000"
947948

948-
for regname, value in values.items():
949+
for regname in values:
950+
value, alias = values[regname]
949951
self.expect(
950952
"register read {}".format(regname),
951953
substrs=["{} = {}".format(regname, value)],
952954
)
955+
if alias:
956+
self.expect(
957+
"register read {}".format(alias),
958+
substrs=["{} = {}".format(regname, value)],
959+
)
953960

954961
for regname, value in fpr_values.items():
955962
self.expect(

‎lldb/test/Shell/Register/Inputs/loongarch64-gp-read.cpp‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
int main() {
2+
asm volatile(
3+
// r0 aka zero is always tied to zero
4+
"li.w $r1, 1\n\t"
5+
"li.w $r2, 2\n\t"
6+
"li.w $r3, 3\n\t"
7+
"li.w $r4, 4\n\t"
8+
"li.w $r5, 5\n\t"
9+
"li.w $r6, 6\n\t"
10+
"li.w $r7, 7\n\t"
11+
"li.w $r8, 8\n\t"
12+
"li.w $r9, 9\n\t"
13+
"li.w $r10, 10\n\t"
14+
"li.w $r11, 11\n\t"
15+
"li.w $r12, 12\n\t"
16+
"li.w $r13, 13\n\t"
17+
"li.w $r14, 14\n\t"
18+
"li.w $r15, 15\n\t"
19+
"li.w $r16, 16\n\t"
20+
"li.w $r17, 17\n\t"
21+
"li.w $r18, 18\n\t"
22+
"li.w $r19, 19\n\t"
23+
"li.w $r20, 20\n\t"
24+
"li.w $r21, 21\n\t"
25+
"li.w $r22, 22\n\t"
26+
"li.w $r23, 23\n\t"
27+
"li.w $r24, 24\n\t"
28+
"li.w $r25, 25\n\t"
29+
"li.w $r26, 26\n\t"
30+
"li.w $r27, 27\n\t"
31+
"li.w $r28, 28\n\t"
32+
"li.w $r29, 29\n\t"
33+
"li.w $r30, 30\n\t"
34+
"li.w $r31, 31\n\t"
35+
"break 5\n\t");
36+
return 0;
37+
}

‎lldb/test/Shell/Register/loongarch64-gp-read.test‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
# REQUIRES: native && target-loongarch64
2+
# RUN: %clangxx_host %p/Inputs/loongarch64-gp-read.cpp -o %t
3+
# RUN: %lldb -b -s %s %t | FileCheck %s
4+
process launch
5+
6+
## Read register using the register's alias.
7+
register read zero ra tp sp a0 a1 a2 a3 a4 a5 a6 a7 t0 t1 t2 t3 t4 t5 t6 t7 t8 r21 fp s0 s1 s2 s3 s4 s5 s6 s7 s8
8+
# CHECK-DAG: r0 = 0x0000000000000000
9+
# CHECK-DAG: r1 = 0x0000000000000001
10+
# CHECK-DAG: r2 = 0x0000000000000002
11+
# CHECK-DAG: r3 = 0x0000000000000003
12+
# CHECK-DAG: r4 = 0x0000000000000004
13+
# CHECK-DAG: r5 = 0x0000000000000005
14+
# CHECK-DAG: r6 = 0x0000000000000006
15+
# CHECK-DAG: r7 = 0x0000000000000007
16+
# CHECK-DAG: r8 = 0x0000000000000008
17+
# CHECK-DAG: r9 = 0x0000000000000009
18+
# CHECK-DAG: r10 = 0x000000000000000a
19+
# CHECK-DAG: r11 = 0x000000000000000b
20+
# CHECK-DAG: r12 = 0x000000000000000c
21+
# CHECK-DAG: r13 = 0x000000000000000d
22+
# CHECK-DAG: r14 = 0x000000000000000e
23+
# CHECK-DAG: r15 = 0x000000000000000f
24+
# CHECK-DAG: r16 = 0x0000000000000010
25+
# CHECK-DAG: r17 = 0x0000000000000011
26+
# CHECK-DAG: r18 = 0x0000000000000012
27+
# CHECK-DAG: r19 = 0x0000000000000013
28+
# CHECK-DAG: r20 = 0x0000000000000014
29+
# CHECK-DAG: r21 = 0x0000000000000015
30+
# CHECK-DAG: r22 = 0x0000000000000016
31+
# CHECK-DAG: r23 = 0x0000000000000017
32+
# CHECK-DAG: r24 = 0x0000000000000018
33+
# CHECK-DAG: r25 = 0x0000000000000019
34+
# CHECK-DAG: r26 = 0x000000000000001a
35+
# CHECK-DAG: r27 = 0x000000000000001b
36+
# CHECK-DAG: r28 = 0x000000000000001c
37+
# CHECK-DAG: r29 = 0x000000000000001d
38+
# CHECK-DAG: r30 = 0x000000000000001e
39+
# CHECK-DAG: r31 = 0x000000000000001f

‎llvm/utils/lit/lit/llvm/config.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,8 @@ def __init__(self, lit_config, config):
175175
features.add("target-riscv64")
176176
elif re.match(r"^riscv32-.*-elf.", target_triple):
177177
features.add("target-riscv32")
178+
elif re.match(r"^loongarch64.*", target_triple):
179+
features.add("target-loongarch64")
178180

179181
if not user_is_root():
180182
features.add("non-root-user")

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