Fix handling of "CSR" references.

Author: efriedma-quic

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -44,6 +44,10 @@
 // |                                   |
 // |-----------------------------------|
 // |                                   |
+// | (Win64 only) callee-saved SVE reg |
+// |                                   |
+// |-----------------------------------|
+// |                                   |
 // | callee-saved gpr registers        | <--.
 // |                                   |    | On Darwin platforms these
 // |- - - - - - - - - - - - - - - - - -|    | callee saves are swapped,
@@ -2877,11 +2881,11 @@ StackOffset AArch64FrameLowering::resolveFrameOffsetReference(
     StackOffset SVECalleeSavedStack =
         StackOffset::getScalable(AFI->getSVECalleeSavedStackSize());
     if (UseFP) {
-      if (!(isFixed || isCSR))
+      if (!isFixed)
         ScalableOffset = SVECalleeSavedStack - SVEStackSize;
       else
         ScalableOffset = SVECalleeSavedStack;
-    } else if (!UseFP && (isFixed || isCSR)) {
+    } else if (!UseFP && isFixed) {
       ScalableOffset = SVEStackSize;
     }
   } else {

llvm/test/CodeGen/AArch64/win-sve.ll

@@ -1228,3 +1228,81 @@ define void @f10(i64 %n, <vscale x 2 x i64> %x) "frame-pointer"="all" {
   call void @g10(ptr %p1, ptr %p2)
   ret void
 }
+
+; Check handling of alloca allocated into CSR space, no frame pointer.
+define i32 @f11(double %d, <vscale x 4 x i32> %vs) "aarch64_pstate_sm_compatible" {
+; CHECK-LABEL: f11:
+; CHECK:       .seh_proc f11
+; CHECK-NEXT:  // %bb.0: // %entry
+; CHECK-NEXT:    addvl sp, sp, #-1
+; CHECK-NEXT:    .seh_allocz 1
+; CHECK-NEXT:    str z8, [sp] // 16-byte Folded Spill
+; CHECK-NEXT:    .seh_save_zreg z8, 0
+; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT:    .seh_save_reg_x x30, 16
+; CHECK-NEXT:    .seh_endprologue
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    //APP
+; CHECK-NEXT:    //NO_APP
+; CHECK-NEXT:    str d0, [sp, #8]
+; CHECK-NEXT:    .seh_startepilogue
+; CHECK-NEXT:    ldr x30, [sp] // 8-byte Folded Reload
+; CHECK-NEXT:    .seh_save_reg x30, 0
+; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    .seh_stackalloc 16
+; CHECK-NEXT:    ldr z8, [sp] // 16-byte Folded Reload
+; CHECK-NEXT:    .seh_save_zreg z8, 0
+; CHECK-NEXT:    addvl sp, sp, #1
+; CHECK-NEXT:    .seh_allocz 1
+; CHECK-NEXT:    .seh_endepilogue
+; CHECK-NEXT:    ret
+; CHECK-NEXT:    .seh_endfunclet
+; CHECK-NEXT:    .seh_endproc
+entry:
+  %a = alloca double
+  tail call void asm sideeffect "", "~{d8}"() #1
+  store double %d, ptr %a
+  ret i32 0
+}
+
+; Check handling of alloca allocated into CSR space, with frame pointer.
+define i32 @f12(double %d, <vscale x 4 x i32> %vs) "frame-pointer"="all" {
+; CHECK-LABEL: f12:
+; CHECK:       .seh_proc f12
+; CHECK-NEXT:  // %bb.0: // %entry
+; CHECK-NEXT:    addvl sp, sp, #-1
+; CHECK-NEXT:    .seh_allocz 1
+; CHECK-NEXT:    str z8, [sp] // 16-byte Folded Spill
+; CHECK-NEXT:    .seh_save_zreg z8, 0
+; CHECK-NEXT:    str x28, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-NEXT:    .seh_save_reg_x x28, 32
+; CHECK-NEXT:    stp x29, x30, [sp, #8] // 16-byte Folded Spill
+; CHECK-NEXT:    .seh_save_fplr 8
+; CHECK-NEXT:    add x29, sp, #8
+; CHECK-NEXT:    .seh_add_fp 8
+; CHECK-NEXT:    .seh_endprologue
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    //APP
+; CHECK-NEXT:    //NO_APP
+; CHECK-NEXT:    str d0, [x29, #16]
+; CHECK-NEXT:    .seh_startepilogue
+; CHECK-NEXT:    ldp x29, x30, [sp, #8] // 16-byte Folded Reload
+; CHECK-NEXT:    .seh_save_fplr 8
+; CHECK-NEXT:    ldr x28, [sp] // 8-byte Folded Reload
+; CHECK-NEXT:    .seh_save_reg x28, 0
+; CHECK-NEXT:    add sp, sp, #32
+; CHECK-NEXT:    .seh_stackalloc 32
+; CHECK-NEXT:    ldr z8, [sp] // 16-byte Folded Reload
+; CHECK-NEXT:    .seh_save_zreg z8, 0
+; CHECK-NEXT:    addvl sp, sp, #1
+; CHECK-NEXT:    .seh_allocz 1
+; CHECK-NEXT:    .seh_endepilogue
+; CHECK-NEXT:    ret
+; CHECK-NEXT:    .seh_endfunclet
+; CHECK-NEXT:    .seh_endproc
+entry:
+  %a = alloca double
+  tail call void asm sideeffect "", "~{d8},~{x28}"() #1
+  store double %d, ptr %a
+  ret i32 0
+}