[llvm] Use llvm::is_contained (NFC)

Author: kazutakahirata

llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp

@@ -516,8 +516,7 @@ static RelaxAux initRelaxAux(LinkGraph &G) {
   RelaxAux Aux;
   Aux.Config.IsRV32 = G.getTargetTriple().isRISCV32();
   const auto &Features = G.getFeatures().getFeatures();
-  Aux.Config.HasRVC =
-      std::find(Features.begin(), Features.end(), "+c") != Features.end();
+  Aux.Config.HasRVC = llvm::is_contained(Features, "+c");
 
   for (auto &S : G.sections()) {
     if (!shouldRelax(S))

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

@@ -1053,11 +1053,9 @@ bool AArch64ExpandPseudo::expandMultiVecPseudo(
   auto ContiguousRange = ContiguousClass.getRegisters();
   auto StridedRange = StridedClass.getRegisters();
   unsigned Opc;
-  if ((std::find(ContiguousRange.begin(), ContiguousRange.end(),
-                 Tuple.asMCReg()) != std::end(ContiguousRange))) {
+  if (llvm::is_contained(ContiguousRange, Tuple.asMCReg())) {
     Opc = ContiguousOp;
-  } else if ((std::find(StridedRange.begin(), StridedRange.end(),
-                        Tuple.asMCReg()) != std::end(StridedRange))) {
+  } else if (llvm::is_contained(StridedRange, Tuple.asMCReg())) {
     Opc = StridedOpc;
   } else
     llvm_unreachable("Cannot expand Multi-Vector pseudo");

llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

@@ -1152,8 +1152,7 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
       if (Pred.getSUnit()->getInstr()->getOpcode() != AMDGPU::V_PERM_B32_e64)
         continue;
 
-      if (Cand &&
-          std::find(Counted.begin(), Counted.end(), Cand) != Counted.end())
+      if (Cand && llvm::is_contained(Counted, Cand))
         break;
 
       for (auto &Succ : Pred.getSUnit()->Succs) {
@@ -1174,7 +1173,7 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
         }
 
         Cand = VMEMLookup[MI];
-        if (std::find(Counted.begin(), Counted.end(), Cand) != Counted.end()) {
+        if (llvm::is_contained(Counted, Cand)) {
           MissedAny = true;
           break;
         }

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

@@ -355,9 +355,7 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
         int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
         assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
 
-        bool IsCalleeSaveSGPRSpill =
-            std::find(CalleeSavedFIs.begin(), CalleeSavedFIs.end(), FI) !=
-            CalleeSavedFIs.end();
+        bool IsCalleeSaveSGPRSpill = llvm::is_contained(CalleeSavedFIs, FI);
         if (IsCalleeSaveSGPRSpill) {
           // Spill callee-saved SGPRs into physical VGPR lanes.
 

llvm/lib/Transforms/Scalar/SROA.cpp

@@ -3126,8 +3126,7 @@ class llvm::sroa::AllocaSliceRewriter
       if (IsDest) {
         // Update the address component of linked dbg.assigns.
         for (auto *DAI : at::getAssignmentMarkers(&II)) {
-          if (any_of(DAI->location_ops(),
-                     [&](Value *V) { return V == II.getDest(); }) ||
+          if (llvm::is_contained(DAI->location_ops(), II.getDest()) ||
               DAI->getAddress() == II.getDest())
             DAI->replaceVariableLocationOp(II.getDest(), AdjustedPtr);
         }