@@ -16,113 +16,113 @@ define void @f1(i64 %x) nounwind {
1616; TR-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
1717; TR-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
1818; TR-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
19- ; TR-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
20- ; TR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
21- ; TR-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
22- ; TR-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
19+ ; TR-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
20+ ; TR-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
21+ ; TR-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
22+ ; TR-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
2323; TR-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
2424; TR: [[BB7]]:
2525; TR-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
2626; TR-NEXT: ret void
2727; TR: [[TRAP]]:
28- ; TR-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]]
29- ; TR-NEXT: unreachable
28+ ; TR-NEXT: call void @llvm.trap() #[[ATTR2:[0-9]+]], !nosanitize [[META0]]
29+ ; TR-NEXT: unreachable, !nosanitize [[META0]]
3030;
3131; RT-LABEL: define void @f1(
3232; RT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
3333; RT-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
3434; RT-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
35- ; RT-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
36- ; RT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
37- ; RT-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
38- ; RT-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
35+ ; RT-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
36+ ; RT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
37+ ; RT-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
38+ ; RT-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
3939; RT-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
4040; RT: [[BB7]]:
4141; RT-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
4242; RT-NEXT: ret void
4343; RT: [[TRAP]]:
44- ; RT-NEXT: call void @__ubsan_handle_local_out_of_bounds() #[[ATTR0]]
45- ; RT-NEXT: br label %[[BB7]]
44+ ; RT-NEXT: call void @__ubsan_handle_local_out_of_bounds() #[[ATTR0]], !nosanitize [[META0]]
45+ ; RT-NEXT: br label %[[BB7]], !nosanitize [[META0]]
4646;
4747; TR-NOMERGE-LABEL: define void @f1(
4848; TR-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
4949; TR-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
5050; TR-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
51- ; TR-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
52- ; TR-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
53- ; TR-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
54- ; TR-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
51+ ; TR-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
52+ ; TR-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
53+ ; TR-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
54+ ; TR-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
5555; TR-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
5656; TR-NOMERGE: [[BB7]]:
5757; TR-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
5858; TR-NOMERGE-NEXT: ret void
5959; TR-NOMERGE: [[TRAP]]:
60- ; TR-NOMERGE-NEXT: call void @llvm.ubsantrap(i8 3) #[[ATTR2:[0-9]+]]
61- ; TR-NOMERGE-NEXT: unreachable
60+ ; TR-NOMERGE-NEXT: call void @llvm.ubsantrap(i8 3) #[[ATTR2:[0-9]+]], !nosanitize [[META0]]
61+ ; TR-NOMERGE-NEXT: unreachable, !nosanitize [[META0]]
6262;
6363; RT-NOMERGE-LABEL: define void @f1(
6464; RT-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
6565; RT-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
6666; RT-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
67- ; RT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
68- ; RT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
69- ; RT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
70- ; RT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
67+ ; RT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
68+ ; RT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
69+ ; RT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
70+ ; RT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
7171; RT-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
7272; RT-NOMERGE: [[BB7]]:
7373; RT-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
7474; RT-NOMERGE-NEXT: ret void
7575; RT-NOMERGE: [[TRAP]]:
76- ; RT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds() #[[ATTR1:[0-9]+]]
77- ; RT-NOMERGE-NEXT: br label %[[BB7]]
76+ ; RT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds() #[[ATTR1:[0-9]+]], !nosanitize [[META0]]
77+ ; RT-NOMERGE-NEXT: br label %[[BB7]], !nosanitize [[META0]]
7878;
7979; RTABORT-NOMERGE-LABEL: define void @f1(
8080; RTABORT-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
8181; RTABORT-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
8282; RTABORT-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
83- ; RTABORT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
84- ; RTABORT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
85- ; RTABORT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
86- ; RTABORT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
83+ ; RTABORT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
84+ ; RTABORT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
85+ ; RTABORT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
86+ ; RTABORT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
8787; RTABORT-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
8888; RTABORT-NOMERGE: [[BB7]]:
8989; RTABORT-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
9090; RTABORT-NOMERGE-NEXT: ret void
9191; RTABORT-NOMERGE: [[TRAP]]:
92- ; RTABORT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_abort() #[[ATTR2:[0-9]+]]
93- ; RTABORT-NOMERGE-NEXT: unreachable
92+ ; RTABORT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_abort() #[[ATTR2:[0-9]+]], !nosanitize [[META0]]
93+ ; RTABORT-NOMERGE-NEXT: unreachable, !nosanitize [[META0]]
9494;
9595; MINRT-NOMERGE-LABEL: define void @f1(
9696; MINRT-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
9797; MINRT-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
9898; MINRT-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
99- ; MINRT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
100- ; MINRT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
101- ; MINRT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
102- ; MINRT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
99+ ; MINRT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
100+ ; MINRT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
101+ ; MINRT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
102+ ; MINRT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
103103; MINRT-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
104104; MINRT-NOMERGE: [[BB7]]:
105105; MINRT-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
106106; MINRT-NOMERGE-NEXT: ret void
107107; MINRT-NOMERGE: [[TRAP]]:
108- ; MINRT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_minimal() #[[ATTR1:[0-9]+]]
109- ; MINRT-NOMERGE-NEXT: br label %[[BB7]]
108+ ; MINRT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_minimal() #[[ATTR1:[0-9]+]], !nosanitize [[META0]]
109+ ; MINRT-NOMERGE-NEXT: br label %[[BB7]], !nosanitize [[META0]]
110110;
111111; MINRTABORT-NOMERGE-LABEL: define void @f1(
112112; MINRTABORT-NOMERGE-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
113113; MINRTABORT-NOMERGE-NEXT: [[TMP1:%.*]] = mul i64 16, [[X]]
114114; MINRTABORT-NOMERGE-NEXT: [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
115- ; MINRTABORT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0
116- ; MINRTABORT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
117- ; MINRTABORT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
118- ; MINRTABORT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
115+ ; MINRTABORT-NOMERGE-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], 0, !nosanitize [[META0:![0-9]+]]
116+ ; MINRTABORT-NOMERGE-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16, !nosanitize [[META0]]
117+ ; MINRTABORT-NOMERGE-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]], !nosanitize [[META0]]
118+ ; MINRTABORT-NOMERGE-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]], !nosanitize [[META0]]
119119; MINRTABORT-NOMERGE-NEXT: br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
120120; MINRTABORT-NOMERGE: [[BB7]]:
121121; MINRTABORT-NOMERGE-NEXT: [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
122122; MINRTABORT-NOMERGE-NEXT: ret void
123123; MINRTABORT-NOMERGE: [[TRAP]]:
124- ; MINRTABORT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_minimal_abort() #[[ATTR2:[0-9]+]]
125- ; MINRTABORT-NOMERGE-NEXT: unreachable
124+ ; MINRTABORT-NOMERGE-NEXT: call void @__ubsan_handle_local_out_of_bounds_minimal_abort() #[[ATTR2:[0-9]+]], !nosanitize [[META0]]
125+ ; MINRTABORT-NOMERGE-NEXT: unreachable, !nosanitize [[META0]]
126126;
127127 %1 = alloca i128 , i64 %x
128128 %3 = load i128 , ptr %1 , align 4
@@ -154,3 +154,17 @@ define void @f1(i64 %x) nounwind {
154154; MINRTABORT-NOMERGE: attributes #[[ATTR1:[0-9]+]] = { noreturn nounwind }
155155; MINRTABORT-NOMERGE: attributes #[[ATTR2]] = { nomerge noreturn nounwind }
156156;.
157+ ; TR: [[META0]] = !{}
158+ ;.
159+ ; RT: [[META0]] = !{}
160+ ;.
161+ ; TR-NOMERGE: [[META0]] = !{}
162+ ;.
163+ ; RT-NOMERGE: [[META0]] = !{}
164+ ;.
165+ ; RTABORT-NOMERGE: [[META0]] = !{}
166+ ;.
167+ ; MINRT-NOMERGE: [[META0]] = !{}
168+ ;.
169+ ; MINRTABORT-NOMERGE: [[META0]] = !{}
170+ ;.
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