marchid and mimplid can be 0

wangpc-pp · wangpc-pp · commit 8afe59fad4b6 · 2024-11-14T22:17:59.000+08:00
Created using spr 1.3.6-beta.1
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -73,7 +73,7 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) {
 
 bool hasValidCPUModel(StringRef CPU) {
   const CPUInfo *Info = getCPUInfoByName(CPU);
-  return Info && Info->MVendorID && Info->MArchID && Info->MImpID;
+  return Info && Info->MVendorID;
 }
 
 uint32_t getVendorID(StringRef CPU) {

Original file line number	Diff line number	Diff line change
`@@ -73,7 +73,7 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) {`
`73`	`73`
`74`	`74`	`bool hasValidCPUModel(StringRef CPU) {`
`75`	`75`	`const CPUInfo *Info = getCPUInfoByName(CPU);`
`76`		`- return Info && Info->MVendorID && Info->MArchID && Info->MImpID;`
	`76`	`+ return Info && Info->MVendorID;`
`77`	`77`	`}`
`78`	`78`
`79`	`79`	`uint32_t getVendorID(StringRef CPU) {`