use isScalar and isFixedVector

Author: tgymnich

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

@@ -6816,7 +6816,7 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
   LLT TrueTy = MRI.getType(Select->getTrueReg());
 
   // We only do this combine for scalar boolean conditions.
-  if (CondTy != LLT::scalar(1))
+  if (!CondTy.isScalar(1))
     return false;
 
   if (TrueTy.isPointer())

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -2099,7 +2099,7 @@ LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
       const unsigned Offset = (I - 1) * PartSize;
 
       Register SrcReg = MI.getOperand(I).getReg();
-      assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
+      assert(MRI.getType(SrcReg).isScalar(PartSize));
 
       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
 
@@ -6596,7 +6596,7 @@ LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx,
   // If all finite floats fit into the narrowed integer type, we can just swap
   // out the result type. This is practically only useful for conversions from
   // half to at least 16-bits, so just handle the one case.
-  if (SrcTy.getScalarType() != LLT::scalar(16) ||
+  if (!SrcTy.getScalarType().isScalar(16) ||
       NarrowTy.getScalarSizeInBits() < (IsSigned ? 17u : 16u))
     return UnableToLegalize;
 
@@ -7471,7 +7471,7 @@ LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
   const LLT S32 = LLT::scalar(32);
   const LLT S1 = LLT::scalar(1);
 
-  assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
+  assert(MRI.getType(Src).isScalar(64) && MRI.getType(Dst).isScalar(32));
 
   // unsigned cul2f(ulong u) {
   //   uint lz = clz(u);
@@ -7529,7 +7529,7 @@ LegalizerHelper::lowerU64ToF32WithSITOFP(MachineInstr &MI) {
   const LLT S32 = LLT::scalar(32);
   const LLT S1 = LLT::scalar(1);
 
-  assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
+  assert(MRI.getType(Src).isScalar(64) && MRI.getType(Dst).isScalar(32));
 
   // For i64 < INT_MAX we simply reuse SITOFP.
   // Otherwise, divide i64 by 2, round result by ORing with the lowest bit
@@ -7563,7 +7563,7 @@ LegalizerHelper::lowerU64ToF64BitFloatOps(MachineInstr &MI) {
   const LLT S64 = LLT::scalar(64);
   const LLT S32 = LLT::scalar(32);
 
-  assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S64);
+  assert(MRI.getType(Src).isScalar(64) && MRI.getType(Dst).isScalar(64));
 
   // We create double value from 32 bit parts with 32 exponent difference.
   // Note that + and - are float operations that adjust the implicit leading
@@ -7595,25 +7595,25 @@ LegalizerHelper::lowerU64ToF64BitFloatOps(MachineInstr &MI) {
 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) {
   auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
 
-  if (SrcTy == LLT::scalar(1)) {
+  if (SrcTy.isScalar(1)) {
     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
     MIRBuilder.buildSelect(Dst, Src, True, False);
     MI.eraseFromParent();
     return Legalized;
   }
 
-  if (SrcTy != LLT::scalar(64))
+  if (!SrcTy.isScalar(64))
     return UnableToLegalize;
 
-  if (DstTy == LLT::scalar(32))
+  if (DstTy.isScalar(32))
     // TODO: SelectionDAG has several alternative expansions to port which may
     // be more reasonable depending on the available instructions. We also need
     // a more advanced mechanism to choose an optimal version depending on
     // target features such as sitofp or CTLZ availability.
     return lowerU64ToF32WithSITOFP(MI);
 
-  if (DstTy == LLT::scalar(64))
+  if (DstTy.isScalar(64))
     return lowerU64ToF64BitFloatOps(MI);
 
   return UnableToLegalize;
@@ -7626,18 +7626,18 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) {
   const LLT S32 = LLT::scalar(32);
   const LLT S1 = LLT::scalar(1);
 
-  if (SrcTy == S1) {
+  if (SrcTy.isScalar(1)) {
     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
     MIRBuilder.buildSelect(Dst, Src, True, False);
     MI.eraseFromParent();
     return Legalized;
   }
 
-  if (SrcTy != S64)
+  if (!SrcTy.isScalar(64))
     return UnableToLegalize;
 
-  if (DstTy == S32) {
+  if (DstTy.isScalar(32)) {
     // signed cl2f(long l) {
     //   long s = l >> 63;
     //   float r = cul2f((l + s) ^ s);
@@ -7664,12 +7664,10 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) {
 
 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) {
   auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
-  const LLT S64 = LLT::scalar(64);
-  const LLT S32 = LLT::scalar(32);
 
-  if (SrcTy != S64 && SrcTy != S32)
+  if (!SrcTy.isScalar(64) && !SrcTy.isScalar(32))
     return UnableToLegalize;
-  if (DstTy != S32 && DstTy != S64)
+  if (!DstTy.isScalar(32) && !DstTy.isScalar(64))
     return UnableToLegalize;
 
   // FPTOSI gives same result as FPTOUI for positive signed integers.
@@ -7704,11 +7702,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) {
 
 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) {
   auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
-  const LLT S64 = LLT::scalar(64);
-  const LLT S32 = LLT::scalar(32);
 
   // FIXME: Only f32 to i64 conversions are supported.
-  if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64)
+  if (!SrcTy.getScalarType().isScalar(32) || !DstTy.getScalarType().isScalar(64))
     return UnableToLegalize;
 
   // Expand f32 -> i64 conversion
@@ -7873,8 +7869,8 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
   const LLT S32 = LLT::scalar(32);
 
   auto [Dst, Src] = MI.getFirst2Regs();
-  assert(MRI.getType(Dst).getScalarType() == LLT::scalar(16) &&
-         MRI.getType(Src).getScalarType() == LLT::scalar(64));
+  assert(MRI.getType(Dst).getScalarType().isScalar(16) &&
+         MRI.getType(Src).getScalarType().isScalar(64));
 
   if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
     return UnableToLegalize;
@@ -7985,10 +7981,8 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) {
   auto [DstTy, SrcTy] = MI.getFirst2LLTs();
-  const LLT S64 = LLT::scalar(64);
-  const LLT S16 = LLT::scalar(16);
 
-  if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64)
+  if (DstTy.getScalarType().isScalar(16) && SrcTy.getScalarType().isScalar(64))
     return lowerFPTRUNC_F64_TO_F16(MI);
 
   return UnableToLegalize;
@@ -9263,7 +9257,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
 
     // The condition was potentially zero extended before, but we want a sign
     // extended boolean.
-    if (MaskTy != LLT::scalar(1))
+    if (!MaskTy.isScalar(1))
       MaskElt = MIRBuilder.buildSExtInReg(MaskTy, MaskElt, 1).getReg(0);
 
     // Continue the sign extension (or truncate) to match the data type.

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

@@ -72,7 +72,7 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
     if (TRI->isSGPRReg(MRI, PhysReg)) {
       LLT Ty = MRI.getType(ExtReg);
       LLT S32 = LLT::scalar(32);
-      if (Ty != S32) {
+      if (!Ty.isScalar(32)) {
         // FIXME: We should probably support readfirstlane intrinsics with all
         // legal 32-bit types.
         assert(Ty.getSizeInBits() == 32);

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp

@@ -409,7 +409,7 @@ static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
   const MachineInstr *Def = MRI.getVRegDef(Reg);
   if (Def->getOpcode() == TargetOpcode::G_FPEXT) {
     Register SrcReg = Def->getOperand(1).getReg();
-    return MRI.getType(SrcReg) == LLT::scalar(16);
+    return MRI.getType(SrcReg).isScalar(16);
   }
 
   if (Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
@@ -428,7 +428,7 @@ bool AMDGPUCombinerHelper::matchExpandPromotedF16FMed3(MachineInstr &MI,
                                                        Register Src2) const {
   assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC);
   Register SrcReg = MI.getOperand(1).getReg();
-  if (!MRI.hasOneNonDBGUse(SrcReg) || MRI.getType(SrcReg) != LLT::scalar(32))
+  if (!MRI.hasOneNonDBGUse(SrcReg) || !MRI.getType(SrcReg).isScalar(32))
     return false;
 
   return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) &&

llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp

@@ -87,7 +87,7 @@ DivergenceLoweringHelper::DivergenceLoweringHelper(
 
 // _(s1) -> SReg_32/64(s1)
 void DivergenceLoweringHelper::markAsLaneMask(Register DstReg) const {
-  assert(MRI->getType(DstReg) == LLT::scalar(1));
+  assert(MRI->getType(DstReg).isScalar(1));
 
   if (MRI->getRegClassOrNull(DstReg)) {
     if (MRI->constrainRegClass(DstReg, ST->getBoolRC()))
@@ -100,13 +100,11 @@ void DivergenceLoweringHelper::markAsLaneMask(Register DstReg) const {
 
 void DivergenceLoweringHelper::getCandidatesForLowering(
     SmallVectorImpl<MachineInstr *> &Vreg1Phis) const {
-  LLT S1 = LLT::scalar(1);
-
   // Add divergent i1 phis to the list
   for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB.phis()) {
       Register Dst = MI.getOperand(0).getReg();
-      if (MRI->getType(Dst) == S1 && MUI->isDivergent(Dst))
+      if (MRI->getType(Dst).isScalar(1) && MUI->isDivergent(Dst))
         Vreg1Phis.push_back(&MI);
     }
   }

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

@@ -105,7 +105,7 @@ bool AMDGPUInstructionSelector::constrainCopyLikeIntrin(MachineInstr &MI,
   MachineOperand &Src = MI.getOperand(1);
 
   // TODO: This should be legalized to s32 if needed
-  if (MRI->getType(Dst.getReg()) == LLT::scalar(1))
+  if (MRI->getType(Dst.getReg()).isScalar(1))
     return false;
 
   const TargetRegisterClass *DstRC
@@ -293,7 +293,7 @@ bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
   // - divergent S1 G_PHI should go through lane mask merging algorithm
   //   and be fully inst-selected in AMDGPUGlobalISelDivergenceLowering
   // - uniform S1 G_PHI should be lowered into S32 G_PHI in AMDGPURegBankSelect
-  if (DefTy == LLT::scalar(1))
+  if (DefTy.isScalar(1))
     return false;
 
   // TODO: Verify this doesn't have insane operands (i.e. VGPR to SGPR copy)
@@ -733,9 +733,9 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
   // Selection logic below is for V2S16 only.
   // For G_BUILD_VECTOR_TRUNC, additionally check that the operands are s32.
   Register Dst = MI.getOperand(0).getReg();
-  if (MRI->getType(Dst) != LLT::fixed_vector(2, 16) ||
+  if (!MRI->getType(Dst).isFixedVector(2, 16) ||
       (MI.getOpcode() == AMDGPU::G_BUILD_VECTOR_TRUNC &&
-       SrcTy != LLT::scalar(32)))
+       !SrcTy.isScalar(32)))
     return selectImpl(MI, *CoverageInfo);
 
   const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI);
@@ -1073,9 +1073,9 @@ bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const {
 
   LLT Ty = MRI->getType(Dst0);
   unsigned Opc;
-  if (Ty == LLT::scalar(32))
+  if (Ty.isScalar(32))
     Opc = AMDGPU::V_DIV_SCALE_F32_e64;
-  else if (Ty == LLT::scalar(64))
+  else if (Ty.isScalar(64))
     Opc = AMDGPU::V_DIV_SCALE_F64_e64;
   else
     return false;
@@ -2387,11 +2387,10 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
   Register SrcReg = I.getOperand(1).getReg();
   const LLT DstTy = MRI->getType(DstReg);
   const LLT SrcTy = MRI->getType(SrcReg);
-  const LLT S1 = LLT::scalar(1);
 
   const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
   const RegisterBank *DstRB;
-  if (DstTy == S1) {
+  if (DstTy.isScalar(1)) {
     // This is a special case. We don't treat s1 for legalization artifacts as
     // vcc booleans.
     DstRB = SrcRB;
@@ -2429,7 +2428,7 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
     return true;
   }
 
-  if (DstTy == LLT::fixed_vector(2, 16) && SrcTy == LLT::fixed_vector(2, 32)) {
+  if (DstTy.isFixedVector(2, 16) && SrcTy.isFixedVector(2, 32)) {
     MachineBasicBlock *MBB = I.getParent();
     const DebugLoc &DL = I.getDebugLoc();
 
@@ -2721,8 +2720,7 @@ static bool isExtractHiElt(MachineRegisterInfo &MRI, Register In,
   if (Shuffle->getOpcode() != AMDGPU::G_SHUFFLE_VECTOR)
     return false;
 
-  assert(MRI.getType(Shuffle->getOperand(0).getReg()) ==
-         LLT::fixed_vector(2, 16));
+  assert(MRI.getType(Shuffle->getOperand(0).getReg()).isFixedVector(2, 16));
 
   ArrayRef<int> Mask = Shuffle->getOperand(3).getShuffleMask();
   assert(Mask.size() == 2);
@@ -2746,8 +2744,8 @@ bool AMDGPUInstructionSelector::selectG_FPEXT(MachineInstr &I) const {
 
   Register Src = I.getOperand(1).getReg();
 
-  if (MRI->getType(Dst) == LLT::scalar(32) &&
-      MRI->getType(Src) == LLT::scalar(16)) {
+  if (MRI->getType(Dst).isScalar(32) &&
+      MRI->getType(Src).isScalar(16)) {
     if (isExtractHiElt(*MRI, Src, Src)) {
       MachineBasicBlock *BB = I.getParent();
       BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_CVT_HI_F32_F16), Dst)
@@ -2775,7 +2773,7 @@ bool AMDGPUInstructionSelector::selectG_FNEG(MachineInstr &MI) const {
   Register Dst = MI.getOperand(0).getReg();
   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);
   if (DstRB->getID() != AMDGPU::SGPRRegBankID ||
-      MRI->getType(Dst) != LLT::scalar(64))
+      !MRI->getType(Dst).isScalar(64))
     return false;
 
   Register Src = MI.getOperand(1).getReg();
@@ -2821,7 +2819,7 @@ bool AMDGPUInstructionSelector::selectG_FABS(MachineInstr &MI) const {
   Register Dst = MI.getOperand(0).getReg();
   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);
   if (DstRB->getID() != AMDGPU::SGPRRegBankID ||
-      MRI->getType(Dst) != LLT::scalar(64))
+      !MRI->getType(Dst).isScalar(64))
     return false;
 
   Register Src = MI.getOperand(1).getReg();
@@ -2993,7 +2991,7 @@ bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
   // RegBankSelect knows what it's doing if the branch condition is scc, even
   // though it currently does not.
   if (!isVCC(CondReg, *MRI)) {
-    if (MRI->getType(CondReg) != LLT::scalar(32))
+    if (!MRI->getType(CondReg).isScalar(32))
       return false;
 
     CondPhysReg = AMDGPU::SCC;
@@ -3456,15 +3454,15 @@ bool AMDGPUInstructionSelector::selectBufferLoadLds(MachineInstr &MI) const {
 static Register matchZeroExtendFromS32(MachineRegisterInfo &MRI, Register Reg) {
   Register ZExtSrc;
   if (mi_match(Reg, MRI, m_GZExt(m_Reg(ZExtSrc))))
-    return MRI.getType(ZExtSrc) == LLT::scalar(32) ? ZExtSrc : Register();
+    return MRI.getType(ZExtSrc).isScalar(32) ? ZExtSrc : Register();
 
   // Match legalized form %zext = G_MERGE_VALUES (s32 %x), (s32 0)
   const MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
   if (Def->getOpcode() != AMDGPU::G_MERGE_VALUES)
     return Register();
 
   assert(Def->getNumOperands() == 3 &&
-         MRI.getType(Def->getOperand(0).getReg()) == LLT::scalar(64));
+         MRI.getType(Def->getOperand(0).getReg()).isScalar(64));
   if (mi_match(Def->getOperand(2).getReg(), MRI, m_ZeroInt())) {
     return Def->getOperand(1).getReg();
   }
@@ -4054,7 +4052,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
     // This is a workaround. For extension from type i1, `selectImpl()` uses
     // patterns from TD file and generates an illegal VGPR to SGPR COPY as type
     // i1 can only be hold in a SGPR class.
-    if (MRI->getType(I.getOperand(1).getReg()) != LLT::scalar(1) &&
+    if (!MRI->getType(I.getOperand(1).getReg()).isScalar(1) &&
         selectImpl(I, *CoverageInfo))
       return true;
     return selectG_SZA_EXT(I);
@@ -4287,7 +4285,7 @@ AMDGPUInstructionSelector::selectVOP3PModsImpl(
   if (MI->getOpcode() == AMDGPU::G_FNEG &&
       // It's possible to see an f32 fneg here, but unlikely.
       // TODO: Treat f32 fneg as only high bit.
-      MRI.getType(Src) == LLT::fixed_vector(2, 16)) {
+      MRI.getType(Src).isFixedVector(2, 16)) {
     Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
     Src = MI->getOperand(1).getReg();
     MI = MRI.getVRegDef(Src);
@@ -5785,7 +5783,7 @@ AMDGPUInstructionSelector::selectSMRDBufferSgprImm(MachineOperand &Root) const {
   if (!EncodedOffset)
     return std::nullopt;
 
-  assert(MRI->getType(SOffset) == LLT::scalar(32));
+  assert(MRI->getType(SOffset).isScalar(32));
   return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },
            [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}};
 }
@@ -5800,7 +5798,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
   std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
 
   if (mi_match(Src, *MRI, m_GFPExt(m_Reg(Src)))) {
-    assert(MRI->getType(Src) == LLT::scalar(16));
+    assert(MRI->getType(Src).isScalar(16));
 
     // Only change Src if src modifier could be gained. In such cases new Src
     // could be sgpr but this does not violate constant bus restriction for