Refactor implementation of isIgnoredCVReg.

Author: efriedma-quic

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -1243,6 +1243,10 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
   getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const {
     return {};
   }
+
+  // Whether this register should be ignored when generating CodeView debug
+  // info, because it's a known there is no mapping available.
+  virtual bool isIgnoredCVReg(MCRegister LLVMReg) const { return false; }
 };
 
 //===----------------------------------------------------------------------===//

llvm/include/llvm/MC/MCRegisterInfo.h

@@ -191,7 +191,6 @@ class LLVM_ABI MCRegisterInfo {
   const DwarfLLVMRegPair *EHDwarf2LRegs;      // Dwarf to LLVM regs mapping EH
   DenseMap<MCRegister, int> L2SEHRegs;        // LLVM to SEH regs mapping
   DenseMap<MCRegister, int> L2CVRegs;         // LLVM to CV regs mapping
-  DenseSet<MCRegister> IgnoredCVRegs;
 
   mutable std::vector<std::vector<MCPhysReg>> RegAliasesCache;
   ArrayRef<MCPhysReg> getCachedAliasesOf(MCRegister R) const;
@@ -355,12 +354,6 @@ class LLVM_ABI MCRegisterInfo {
     L2CVRegs[LLVMReg] = CVReg;
   }
 
-  void ignoreCVReg(MCRegister LLVMReg) { IgnoredCVRegs.insert(LLVMReg); }
-
-  bool isIgnoredCVReg(MCRegister LLVMReg) const {
-    return IgnoredCVRegs.contains(LLVMReg);
-  }
-
   /// This method should return the register where the return
   /// address can be found.
   MCRegister getRARegister() const {

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

@@ -1370,3 +1370,8 @@ bool AArch64RegisterInfo::shouldAnalyzePhysregInMachineLoopInfo(
     MCRegister R) const {
   return R == AArch64::VG;
 }
+
+bool AArch64RegisterInfo::isIgnoredCVReg(MCRegister LLVMReg) const {
+  return (LLVMReg >= AArch64::Z0 && LLVMReg <= AArch64::Z31) ||
+         (LLVMReg >= AArch64::P0 && LLVMReg <= AArch64::P15);
+}

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

@@ -154,6 +154,8 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
                         SmallVectorImpl<uint64_t> &Ops) const override;
 
   bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const override;
+
+  virtual bool isIgnoredCVReg(MCRegister LLVMReg) const override;
 };
 
 } // end namespace llvm

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

@@ -302,20 +302,6 @@ void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
   };
   for (const auto &I : RegMap)
     MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
-  static constexpr MCRegister IgnoredRegs[] = {
-      AArch64::Z0,  AArch64::Z1,  AArch64::Z2,  AArch64::Z3,  AArch64::Z4,
-      AArch64::Z5,  AArch64::Z6,  AArch64::Z7,  AArch64::Z8,  AArch64::Z9,
-      AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14,
-      AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
-      AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24,
-      AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29,
-      AArch64::Z30, AArch64::Z31, AArch64::P0,  AArch64::P1,  AArch64::P2,
-      AArch64::P3,  AArch64::P4,  AArch64::P5,  AArch64::P6,  AArch64::P7,
-      AArch64::P8,  AArch64::P9,  AArch64::P10, AArch64::P11, AArch64::P12,
-      AArch64::P13, AArch64::P14, AArch64::P15,
-  };
-  for (const auto &R : IgnoredRegs)
-    MRI->ignoreCVReg(R);
 }
 
 bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) {