Fix some suggested changes

Change-Id: Idd3deec94bd324b2ab2b3fbc57bec16426673ad2

Author: hchandel

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -347,7 +347,7 @@ static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
                                              const MCDisassembler *Decoder) {
   assert(isUInt<Width>(Imm) && "Invalid immediate");
 
-  if (Imm < LowerBound)
+  if ((Imm + 1) < LowerBound)
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(Imm + 1));

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

@@ -400,7 +400,8 @@ RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
     return (Res - 1);
   }
 
-  return getImmOpValue(MI, OpNo, Fixups, STI);
+  llvm_unreachable("Unhandled expression!");
+  return 0;
 }
 
 uint64_t

llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

@@ -125,10 +125,10 @@ class QCIBitManipRII<bits<3> funct3, bits<2> funct2,
                   (ins InTyRs1:$rs1, uimm5_plus1:$width, uimm5:$shamt),
                   opcodestr, "$rd, $rs1, $width, $shamt"> {
   bits<5> shamt;
-  bits<6> width;
+  bits<5> width;
 
   let Inst{31-30} = funct2;
-  let Inst{29-25} = width{4-0};
+  let Inst{29-25} = width;
   let Inst{24-20} = shamt;
 }
 
@@ -406,10 +406,10 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
                              "$rd, $imm5, $width, $shamt"> {
     bits<5> imm5;
     bits<5> shamt;
-    bits<6> width;
+    bits<5> width;
     let rs1 = imm5;
     let Inst{31-30} = 0b00;
-    let Inst{29-25} = width{4-0};
+    let Inst{29-25} = width;
     let Inst{24-20} = shamt;
   }
   def QC_INSB : QCIBitManipRII<0b001, 0b01, GPR, "qc.insb">;
@@ -443,7 +443,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
     bits<5> rd;
     bits<5> width;
     let Constraints = "$rd = $rd_wb";
-    let Inst{6-2} = width{4-0};
+    let Inst{6-2} = width;
     let Inst{11-7} = rd;
     let Inst{12} = 0b1;
   }

llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt

@@ -1,4 +1,6 @@
 # RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+experimental-xqciac %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+experimental-xqcibm %s \
+# RUN: | FileCheck -check-prefixes=CHECK-XQCIBM  %s
 
 [0x00,0x00]
 # CHECK: unimp
@@ -8,3 +10,6 @@
 
 [0x00,0x00]
 # CHECK: unimp
+
+[0x92,0x17]
+# CHECK-XQCIBM-NOT: qc.c.extu a5, 4