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arsenmarsenm
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AMDGPU: Use RegisterOperand for MIMG vaddr classes
This reduces the diff in a future patch.
1 parent 343186d commit 8c2cc9a

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3 files changed

+78
-58
lines changed

3 files changed

+78
-58
lines changed

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td‎

Lines changed: 58 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -272,13 +272,13 @@ class MIMGNSAHelper<int num_addrs,
272272
!if(!le(num_addrs, 13), 3, ?))));
273273
}
274274

275-
class PartialNSAHelper<int num_addrs, int max_addr, RegisterClass LastAddrRC>
275+
class PartialNSAHelper<int num_addrs, int max_addr, RegisterOperand LastAddrRC>
276276
: NSAHelper<> {
277277

278-
list<RegisterClass> addr_types =
278+
list<RegisterOperand> addr_types =
279279
!if(!ge(num_addrs, max_addr),
280-
!listconcat(!listsplat(VGPR_32, !sub(max_addr, 1)), [LastAddrRC]),
281-
!listsplat(VGPR_32, num_addrs));
280+
!listconcat(!listsplat(VGPROp_32, !sub(max_addr, 1)), [LastAddrRC]),
281+
!listsplat(VGPROp_32, num_addrs));
282282

283283
int VAddrCount = !if(!gt(num_addrs, max_addr), max_addr, num_addrs);
284284
list<string> AddrAsmNames = !foreach(i, !range(VAddrCount), "vaddr" # i);
@@ -359,7 +359,7 @@ class MIMG_gfx11<int op, dag outs, string dns = "">
359359
// Note that 1-dword addresses always use non-NSA variants.
360360
class MIMG_nsa_gfx11<int op, dag outs, int num_addrs, string dns="",
361361
list<RegisterClass> addr_types=[],
362-
RegisterClass LastAddrRC = VGPR_32>
362+
RegisterOperand LastAddrRC = VGPROp_32>
363363
: MIMG<outs, dns>, MIMGe_gfx11<op> {
364364
let SubtargetPredicate = isGFX11Only;
365365
let AssemblerPredicate = isGFX11Only;
@@ -400,7 +400,7 @@ class VIMAGE_gfx12<int op, dag outs, int num_addrs, string dns="",
400400
}
401401

402402
class VSAMPLE_gfx12<int op, dag outs, int num_addrs, string dns="",
403-
RegisterClass Addr3RC>
403+
RegisterOperand Addr3RC>
404404
: VSAMPLE<outs, dns>, VSAMPLEe<op> {
405405
let SubtargetPredicate = isGFX12Plus;
406406
let AssemblerPredicate = isGFX12Plus;
@@ -421,7 +421,7 @@ class VSAMPLE_gfx12<int op, dag outs, int num_addrs, string dns="",
421421

422422
class MIMG_NoSampler_Helper <mimgopc op, string asm,
423423
RegisterOperand dst_rc,
424-
RegisterClass addr_rc,
424+
RegisterOperand addr_rc,
425425
string dns="">
426426
: MIMG_gfx6789 <op.GFX10M, (outs dst_rc:$vdata), dns> {
427427
let InOperandList = !con((ins addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
@@ -434,10 +434,10 @@ class MIMG_NoSampler_Helper <mimgopc op, string asm,
434434

435435
class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm,
436436
RegisterOperand dst_rc,
437-
RegisterClass addr_rc,
437+
RegisterOperand addr_rc,
438438
string dns="">
439439
: MIMG_gfx90a <op.GFX10M, (outs getAlign2RegOp<dst_rc>.ret:$vdata), dns> {
440-
let InOperandList = !con((ins addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
440+
let InOperandList = !con((ins getAlign2RegOp<addr_rc>.ret:$vaddr, SReg_256_XNULL:$srsrc,
441441
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
442442
R128A16:$r128, LWE:$lwe, DA:$da),
443443
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -446,7 +446,7 @@ class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm,
446446
}
447447

448448
class MIMG_NoSampler_gfx10<mimgopc op, string opcode,
449-
RegisterOperand DataRC, RegisterClass AddrRC,
449+
RegisterOperand DataRC, RegisterOperand AddrRC,
450450
string dns="">
451451
: MIMG_gfx10<op.GFX10M, (outs DataRC:$vdata), dns> {
452452
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
@@ -471,7 +471,7 @@ class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode,
471471
}
472472

473473
class MIMG_NoSampler_gfx11<mimgopc op, string opcode,
474-
RegisterOperand DataRC, RegisterClass AddrRC,
474+
RegisterOperand DataRC, RegisterOperand AddrRC,
475475
string dns="">
476476
: MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> {
477477
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
@@ -508,7 +508,7 @@ class VIMAGE_NoSampler_gfx12<mimgopc op, string opcode,
508508
}
509509

510510
class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
511-
int num_addrs, RegisterClass Addr3RC = VGPR_32,
511+
int num_addrs, RegisterOperand Addr3RC = VGPROp_32,
512512
string dns="">
513513
: VSAMPLE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns, Addr3RC> {
514514
let InOperandList = !con(AddrIns,
@@ -525,7 +525,7 @@ class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
525525
}
526526

527527
class VSAMPLE_Sampler_nortn_gfx12<mimgopc op, string opcode,
528-
int num_addrs, RegisterClass Addr3RC = VGPR_32,
528+
int num_addrs, RegisterOperand Addr3RC = VGPROp_32,
529529
string dns="">
530530
: VSAMPLE_gfx12<op.GFX12, (outs), num_addrs, dns, Addr3RC> {
531531
let InOperandList = !con(AddrIns,
@@ -550,16 +550,16 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
550550
let VAddrDwords = 1 in {
551551
let ssamp = 0 in {
552552
if op.HAS_GFX10M then {
553-
def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
553+
def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPROp_32,
554554
!if(enableDisasm, "GFX8", "")>;
555555
if !not(ExtendedImageInst) then
556-
def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32,
556+
def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPROp_32,
557557
!if(enableDisasm, "GFX90A", "")>;
558-
def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32,
558+
def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPROp_32,
559559
!if(enableDisasm, "GFX10", "")>;
560560
}
561561
if op.HAS_GFX11 then {
562-
def _V1_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPR_32,
562+
def _V1_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPROp_32,
563563
!if(enableDisasm, "GFX11", "")>;
564564
}
565565
}
@@ -576,14 +576,14 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
576576
let VAddrDwords = 2 in {
577577
let ssamp = 0 in {
578578
if op.HAS_GFX10M then {
579-
def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>;
579+
def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPROp_64>;
580580
if !not(ExtendedImageInst) then
581-
def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64_Align2>;
582-
def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>;
581+
def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPROp_64_Align2>;
582+
def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPROp_64>;
583583
def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>;
584584
}
585585
if op.HAS_GFX11 then {
586-
def _V2_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_64>;
586+
def _V2_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPROp_64>;
587587
def _V2_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 2>;
588588
}
589589
}
@@ -600,14 +600,14 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
600600
let VAddrDwords = 3 in {
601601
let ssamp = 0 in {
602602
if op.HAS_GFX10M then {
603-
def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>;
603+
def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPROp_96>;
604604
if !not(ExtendedImageInst) then
605-
def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96_Align2>;
606-
def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>;
605+
def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPROp_96_Align2>;
606+
def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPROp_96>;
607607
def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>;
608608
}
609609
if op.HAS_GFX11 then {
610-
def _V3_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_96>;
610+
def _V3_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPROp_96>;
611611
def _V3_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 3>;
612612
}
613613
}
@@ -624,23 +624,23 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
624624
let VAddrDwords = 4 in {
625625
let ssamp = 0 in {
626626
if op.HAS_GFX10M then {
627-
def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>;
627+
def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPROp_128>;
628628
if !not(ExtendedImageInst) then
629-
def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128_Align2>;
630-
def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>;
629+
def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPROp_128_Align2>;
630+
def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPROp_128>;
631631
def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4,
632632
!if(enableDisasm, "GFX10", "")>;
633633
}
634634
if op.HAS_GFX11 then {
635-
def _V4_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_128>;
635+
def _V4_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPROp_128>;
636636
def _V4_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 4,
637637
!if(enableDisasm, "GFX11", "")>;
638638
}
639639
}
640640
if op.HAS_GFX12 then {
641641
if isVSample then {
642642
let samp = 0 in
643-
def _V4_gfx12 : VSAMPLE_Sampler_gfx12<op, asm, dst_rc, 4, VGPR_32,
643+
def _V4_gfx12 : VSAMPLE_Sampler_gfx12<op, asm, dst_rc, 4, VGPROp_32,
644644
!if(enableDisasm, "GFX12", "")>;
645645
}
646646
else {
@@ -1128,7 +1128,7 @@ multiclass MIMG_Atomic_Renamed <mimgopc op, string asm, string renamed,
11281128
: MIMG_Atomic <op, asm, isCmpSwap, isFP, renamed>;
11291129

11301130
class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterOperand dst_rc,
1131-
RegisterClass src_rc, string dns="">
1131+
RegisterOperand src_rc, string dns="">
11321132
: MIMG_gfx6789 <op.VI, (outs dst_rc:$vdata), dns> {
11331133
let InOperandList = !con((ins src_rc:$vaddr, SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
11341134
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
@@ -1139,7 +1139,7 @@ class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterOperand dst_rc,
11391139
}
11401140

11411141
class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterOperand dst_rc,
1142-
RegisterClass src_rc, string dns="">
1142+
RegisterOperand src_rc, string dns="">
11431143
: MIMG_gfx90a<op.GFX10M, (outs dst_rc:$vdata), dns> {
11441144
let InOperandList = !con((ins src_rc:$vaddr, SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
11451145
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
@@ -1164,7 +1164,7 @@ class MIMG_Sampler_Asm_gfx10p<string opcode, string AsmPrefix, bit HasD16> {
11641164
}
11651165

11661166
class MIMG_Sampler_gfx10<mimgopc op, string opcode,
1167-
RegisterOperand DataRC, RegisterClass AddrRC,
1167+
RegisterOperand DataRC, RegisterOperand AddrRC,
11681168
string dns="">
11691169
: MIMG_gfx10<op.GFX10M, (outs DataRC:$vdata), dns> {
11701170
let InOperandList = MIMG_Sampler_OpList_gfx10p<(ins AddrRC:$vaddr0), BaseOpcode.HasD16>.ret;
@@ -1180,7 +1180,7 @@ class MIMG_Sampler_nsa_gfx10<mimgopc op, string opcode,
11801180
}
11811181

11821182
class MIMG_Sampler_nortn_gfx10<mimgopc op, string opcode,
1183-
RegisterClass AddrRC,
1183+
RegisterOperand AddrRC,
11841184
string dns="">
11851185
: MIMG_gfx10<op.GFX10M, (outs), dns> {
11861186
let InOperandList = MIMG_Sampler_OpList_gfx10p<(ins AddrRC:$vaddr0), BaseOpcode.HasD16>.ret;
@@ -1200,7 +1200,7 @@ class MIMG_Sampler_nortn_nsa_gfx10<mimgopc op, string opcode,
12001200
}
12011201

12021202
class MIMG_Sampler_gfx11<mimgopc op, string opcode,
1203-
RegisterOperand DataRC, RegisterClass AddrRC,
1203+
RegisterOperand DataRC, RegisterOperand AddrRC,
12041204
string dns="">
12051205
: MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> {
12061206
let InOperandList = MIMG_Sampler_OpList_gfx10p<(ins AddrRC:$vaddr0), BaseOpcode.HasD16>.ret;
@@ -1209,15 +1209,15 @@ class MIMG_Sampler_gfx11<mimgopc op, string opcode,
12091209

12101210
class MIMG_Sampler_nsa_gfx11<mimgopc op, string opcode,
12111211
RegisterOperand DataRC, int num_addrs,
1212-
RegisterClass LastVAddrSize, string dns="">
1212+
RegisterOperand LastVAddrSize, string dns="">
12131213
: MIMG_nsa_gfx11<op.GFX11, (outs DataRC:$vdata), num_addrs, dns, [],
12141214
LastVAddrSize> {
12151215
let InOperandList = MIMG_Sampler_OpList_gfx10p<AddrIns, BaseOpcode.HasD16>.ret;
12161216
let AsmString = MIMG_Sampler_Asm_gfx10p<opcode, " $vdata, "#AddrAsm, BaseOpcode.HasD16>.ret;
12171217
}
12181218

12191219
class MIMG_Sampler_nortn_gfx11<mimgopc op, string opcode,
1220-
RegisterClass AddrRC,
1220+
RegisterOperand AddrRC,
12211221
string dns="">
12221222
: MIMG_gfx11<op.GFX11, (outs), dns> {
12231223
let InOperandList = MIMG_Sampler_OpList_gfx10p<(ins AddrRC:$vaddr0), BaseOpcode.HasD16>.ret;
@@ -1227,7 +1227,7 @@ class MIMG_Sampler_nortn_gfx11<mimgopc op, string opcode,
12271227

12281228
class MIMG_Sampler_nortn_nsa_gfx11<mimgopc op, string opcode,
12291229
int num_addrs,
1230-
RegisterClass LastVAddrSize, string dns="">
1230+
RegisterOperand LastVAddrSize, string dns="">
12311231
: MIMG_nsa_gfx11<op.GFX11, (outs), num_addrs, dns, [], LastVAddrSize> {
12321232
let InOperandList = MIMG_Sampler_OpList_gfx10p<AddrIns, BaseOpcode.HasD16>.ret;
12331233
let AsmString = MIMG_Sampler_Asm_gfx10p<opcode, "off, "#AddrAsm, BaseOpcode.HasD16>.ret;
@@ -1237,20 +1237,20 @@ class MIMG_Sampler_nortn_nsa_gfx11<mimgopc op, string opcode,
12371237
class MIMGAddrSize<int dw, bit enable_disasm, int AddrDW = dw> {
12381238
int NumWords = dw;
12391239

1240-
RegisterClass RegClass = !if(!le(AddrDW, 0), ?,
1241-
!if(!eq(AddrDW, 1), VGPR_32,
1242-
!if(!eq(AddrDW, 2), VReg_64,
1243-
!if(!eq(AddrDW, 3), VReg_96,
1244-
!if(!eq(AddrDW, 4), VReg_128,
1245-
!if(!eq(AddrDW, 5), VReg_160,
1246-
!if(!eq(AddrDW, 6), VReg_192,
1247-
!if(!eq(AddrDW, 7), VReg_224,
1248-
!if(!eq(AddrDW, 8), VReg_256,
1249-
!if(!eq(AddrDW, 9), VReg_288,
1250-
!if(!eq(AddrDW, 10), VReg_320,
1251-
!if(!eq(AddrDW, 11), VReg_352,
1252-
!if(!eq(AddrDW, 12), VReg_384,
1253-
!if(!le(AddrDW, 16), VReg_512, ?))))))))))))));
1240+
RegisterOperand RegClass = !if(!le(AddrDW, 0), ?,
1241+
!if(!eq(AddrDW, 1), VGPROp_32,
1242+
!if(!eq(AddrDW, 2), VGPROp_64,
1243+
!if(!eq(AddrDW, 3), VGPROp_96,
1244+
!if(!eq(AddrDW, 4), VGPROp_128,
1245+
!if(!eq(AddrDW, 5), VGPROp_160,
1246+
!if(!eq(AddrDW, 6), VGPROp_192,
1247+
!if(!eq(AddrDW, 7), VGPROp_224,
1248+
!if(!eq(AddrDW, 8), VGPROp_256,
1249+
!if(!eq(AddrDW, 9), VGPROp_288,
1250+
!if(!eq(AddrDW, 10), VGPROp_320,
1251+
!if(!eq(AddrDW, 11), VGPROp_352,
1252+
!if(!eq(AddrDW, 12), VGPROp_384,
1253+
!if(!le(AddrDW, 16), VGPROp_512, ?))))))))))))));
12541254

12551255
// Whether the instruction variant with this vaddr size should be enabled for
12561256
// the auto-generated disassembler.
@@ -1514,8 +1514,10 @@ multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample>
15141514

15151515
class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
15161516
int num_addrs = !if(isBVH8, 11, !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11)));
1517-
RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;
1518-
int VAddrDwords = !srl(RegClass.Size, 5);
1517+
RegisterOperand RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;
1518+
1519+
defvar Size = !cast<SIRegisterClass>(RegClass.RegClass).Size;
1520+
int VAddrDwords = !srl(Size, 5);
15191521

15201522
int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
15211523
RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
@@ -1526,7 +1528,7 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
15261528
true : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]);
15271529
}
15281530

1529-
class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>
1531+
class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterOperand AddrRC>
15301532
: MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "GFX10"> {
15311533
let InOperandList = (ins AddrRC:$vaddr0, SReg_128_XNULL:$srsrc, A16:$a16);
15321534
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
@@ -1540,7 +1542,7 @@ class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs>
15401542
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";
15411543
}
15421544

1543-
class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC>
1545+
class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterOperand AddrRC>
15441546
: MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "GFX11"> {
15451547
let InOperandList = (ins AddrRC:$vaddr0, SReg_128_XNULL:$srsrc, A16:$a16);
15461548
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2596,24 +2596,42 @@ class getAlign2RegOp<RegisterOperand RC> {
25962596
RegisterOperand ret =
25972597
!cond(!eq(RC, VGPROp_16) : VGPROp_16,
25982598
!eq(RC, VGPROp_32) : VGPROp_32,
2599+
25992600
!eq(RC, VGPROp_64) : VGPROp_64_Align2,
26002601
!eq(RC, VGPROp_64_Align1) : VGPROp_64_Align2,
2602+
!eq(RC, VGPROp_64_Align2) : VGPROp_64_Align2,
2603+
26012604
!eq(RC, VGPROp_96) : VGPROp_96_Align2,
26022605
!eq(RC, VGPROp_96_Align1) : VGPROp_96_Align2,
2606+
!eq(RC, VGPROp_96_Align2) : VGPROp_96_Align2,
2607+
26032608
!eq(RC, VGPROp_128) : VGPROp_128_Align2,
26042609
!eq(RC, VGPROp_128_Align1) : VGPROp_128_Align2,
2610+
!eq(RC, VGPROp_128_Align2) : VGPROp_128_Align2,
2611+
26052612
!eq(RC, VGPROp_160) : VGPROp_160_Align2,
26062613
!eq(RC, VGPROp_160_Align1) : VGPROp_160_Align2,
2614+
!eq(RC, VGPROp_160_Align2) : VGPROp_160_Align2,
2615+
26072616
!eq(RC, VGPROp_1024) : VGPROp_1024_Align2,
26082617
!eq(RC, VGPROp_1024_Align1) : VGPROp_1024_Align2,
2618+
!eq(RC, VGPROp_1024_Align2) : VGPROp_1024_Align2,
2619+
26092620
!eq(RC, AVLdSt_32) : AVLdSt_32,
2621+
!eq(RC, AVLdSt_64_Align1) : AVLdSt_64_Align2,
26102622
!eq(RC, AVLdSt_64) : AVLdSt_64_Align2,
2623+
26112624
!eq(RC, AVLdSt_96) : AVLdSt_96_Align2,
2625+
!eq(RC, AVLdSt_96_Align1) : AVLdSt_96_Align1,
26122626
!eq(RC, AVLdSt_96_Align1) : AVLdSt_96_Align2,
2627+
26132628
!eq(RC, AVLdSt_128) : AVLdSt_128_Align2,
26142629
!eq(RC, AVLdSt_128_Align1) : AVLdSt_128_Align2,
2630+
!eq(RC, AVLdSt_128_Align2) : AVLdSt_128_Align2,
2631+
26152632
!eq(RC, AVLdSt_160) : AVLdSt_160_Align2,
2616-
!eq(RC, AVLdSt_160_Align1) : AVLdSt_160_Align2);
2633+
!eq(RC, AVLdSt_160_Align1) : AVLdSt_160_Align2,
2634+
!eq(RC, AVLdSt_160_Align2) : AVLdSt_160_Align2);
26172635
}
26182636

26192637
class getEquivalentAGPROperand<RegisterOperand RC> {

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1327,7 +1327,7 @@ def VGPROp_16 : VGPROp<VGPR_16> {
13271327
}
13281328
def VGPROp_32 : VGPROp<VGPR_32>;
13291329

1330-
foreach size = ["64", "96", "128", "160", "192", "224", "256", "288", "512", "1024"] in {
1330+
foreach size = ["64", "96", "128", "160", "192", "224", "256", "288", "320", "352", "384", "512", "1024"] in {
13311331
def VGPROp_#size : VGPROp<!cast<RegisterClass>("VReg_"#size)>;
13321332
}
13331333

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