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[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension
This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Change-Id: I0472a9b3cd999f0b7d16aa351215cce12a788569
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14 files changed

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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -212,6 +212,7 @@
212212
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
213213
// CHECK-NEXT: xqcisim 0.2 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
214214
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
215+
// CHECK-NEXT: xqcisync 0.2 'Xqcisync' (Qualcomm uC Sync Delay Extension)
215216
// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New)
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// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
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// CHECK-EMPTY:

‎llvm/docs/RISCVUsage.rst‎

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@@ -482,6 +482,9 @@ The current vendor extensions supported are:
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``experimental-Xqcisls``
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LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcisync``
486+
LLVM implements `version 0.2 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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485488
``Xmipscmove``
486489
LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
487490

‎llvm/docs/ReleaseNotes.md‎

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@@ -130,6 +130,8 @@ Changes to the RISC-V Backend
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* Added non-quadratic ``log-vrgather`` cost model for ``vrgather.vv`` instruction
131131
* Adds experimental assembler support for the Qualcomm uC 'Xqcisim` (Simulation Hint)
132132
extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcisync` (Sync Delay)
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extension.
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* Adds assembler support for the 'Zilsd` (Load/Store Pair Instructions)
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extension.
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* Adds assembler support for the 'Zclsd` (Compressed Load/Store Pair Instructions)

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

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@@ -772,6 +772,18 @@ struct RISCVOperand final : public MCParsedAsmOperand {
772772
VK == RISCVMCExpr::VK_None;
773773
}
774774

775+
bool isUImm5Slist() const {
776+
if (!isImm())
777+
return false;
778+
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_None;
779+
int64_t Imm;
780+
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
781+
return IsConstantImm &&
782+
((Imm == 0) || (Imm == 1) || (Imm == 2) || (Imm == 4) ||
783+
(Imm == 8) || (Imm == 16) || (Imm == 15) || (Imm == 31)) &&
784+
VK == RISCVMCExpr::VK_None;
785+
}
786+
775787
bool isUImm8GE32() const {
776788
int64_t Imm;
777789
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_None;
@@ -1655,6 +1667,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
16551667
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5));
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case Match_InvalidUImm5GE6Plus1:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 6, (1 << 5));
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case Match_InvalidUImm5Slist:
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return generateImmOutOfRangeError(
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Operands, ErrorInfo, 0, (1 << 5) - 1,
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"immediate must be one of: 0, 1, 2, 4, 8, 15, 16, 31 in the range ");
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case Match_InvalidUImm6:
16591675
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
16601676
case Match_InvalidUImm7:

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 18 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -370,6 +370,15 @@ static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
370370
return MCDisassembler::Success;
371371
}
372372

373+
static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm,
374+
int64_t Address,
375+
const MCDisassembler *Decoder) {
376+
assert(isUInt<3>(Imm) && "Invalid Slist immediate");
377+
const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
378+
Inst.addOperand(MCOperand::createImm(Slist[Imm]));
379+
return MCDisassembler::Success;
380+
}
381+
373382
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
374383
int64_t Address,
375384
const MCDisassembler *Decoder) {
@@ -663,14 +672,15 @@ static constexpr FeatureBitset XRivosFeatureGroup = {
663672
};
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665674
static constexpr FeatureBitset XqciFeatureGroup = {
666-
RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
667-
RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
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RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
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RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
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RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb,
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RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
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RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
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RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls,
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RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
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RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
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RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
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RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
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RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb,
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RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
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RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
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RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls,
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RISCV::FeatureVendorXqcisync,
674684
};
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676686
static constexpr FeatureBitset XSfVectorGroup = {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

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@@ -299,6 +299,7 @@ enum OperandType : unsigned {
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OPERAND_UIMM5_PLUS1,
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OPERAND_UIMM5_GE6_PLUS1,
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OPERAND_UIMM5_LSB0,
302+
OPERAND_UIMM5_SLIST,
302303
OPERAND_UIMM6,
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OPERAND_UIMM6_LSB0,
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OPERAND_UIMM7,

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp‎

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@@ -84,6 +84,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
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SmallVectorImpl<MCFixup> &Fixups,
8585
const MCSubtargetInfo &STI) const;
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87+
uint64_t getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
88+
SmallVectorImpl<MCFixup> &Fixups,
89+
const MCSubtargetInfo &STI) const;
90+
8791
uint64_t getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
8892
SmallVectorImpl<MCFixup> &Fixups,
8993
const MCSubtargetInfo &STI) const;
@@ -404,6 +408,36 @@ RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
404408
return 0;
405409
}
406410

411+
uint64_t
412+
RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
413+
SmallVectorImpl<MCFixup> &Fixups,
414+
const MCSubtargetInfo &STI) const {
415+
const MCOperand &MO = MI.getOperand(OpNo);
416+
assert(MO.isImm() && "Slist operand must be immediate");
417+
418+
uint64_t Res = MO.getImm();
419+
switch (Res) {
420+
case 0:
421+
return 0;
422+
case 1:
423+
return 1;
424+
case 2:
425+
return 2;
426+
case 4:
427+
return 3;
428+
case 8:
429+
return 4;
430+
case 16:
431+
return 5;
432+
case 15:
433+
return 6;
434+
case 31:
435+
return 7;
436+
default:
437+
llvm_unreachable("Unhandled Slist value!");
438+
}
439+
}
440+
407441
uint64_t
408442
RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
409443
SmallVectorImpl<MCFixup> &Fixups,

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1438,6 +1438,14 @@ def HasVendorXqcisim
14381438
AssemblerPredicate<(all_of FeatureVendorXqcisim),
14391439
"'Xqcisim' (Qualcomm uC Simulation Hint Extension)">;
14401440

1441+
def FeatureVendorXqcisync
1442+
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Sync Delay Extension",
1443+
[FeatureStdExtZca]>;
1444+
def HasVendorXqcisync
1445+
: Predicate<"Subtarget->hasVendorXqcisync()">,
1446+
AssemblerPredicate<(all_of FeatureVendorXqcisync),
1447+
"'Xqcisync' (Qualcomm uC Sync Delay Extension)">;
1448+
14411449
// Rivos Extension(s)
14421450

14431451
def FeatureVendorXRivosVisni

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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Original file line numberDiff line numberDiff line change
@@ -50,6 +50,21 @@ def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
5050
let OperandType = "OPERAND_UIMM5_GE6_PLUS1";
5151
}
5252

53+
def uimm5slist : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
54+
[{return ((Imm == 0) ||
55+
(Imm == 1) ||
56+
(Imm == 2) ||
57+
(Imm == 4) ||
58+
(Imm == 8) ||
59+
(Imm == 16) ||
60+
(Imm == 15) ||
61+
(Imm == 31));}]> {
62+
let ParserMatchClass = UImmAsmOperand<5, "Slist">;
63+
let EncoderMethod = "getImmOpValueSlist";
64+
let DecoderMethod = "decodeUImmSlistOperand";
65+
let OperandType = "OPERAND_UIMM5_SLIST";
66+
}
67+
5368
def uimm10 : RISCVUImmLeafOp<10>;
5469

5570
def uimm11 : RISCVUImmLeafOp<11>;
@@ -364,6 +379,27 @@ class QCISim_RS1<bits<4> imm11_8, string opcodestr>
364379
let imm12 = {imm11_8, 0b00000000};
365380
}
366381

382+
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
383+
class QCISync_UIMM5<bits<4> imm11_8, string opcodestr>
384+
: RVInstI<0b011, OPC_OP_IMM, (outs), (ins uimm5:$imm5), opcodestr, "$imm5">
385+
{
386+
bits<5> imm5;
387+
388+
let rs1 = 0;
389+
let rd = 0;
390+
let imm12 = {imm11_8, 0b000, imm5};
391+
}
392+
393+
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
394+
class QCIRVInst16CBSYNC<bits<3> imm5_func2, string OpcodeStr>
395+
: RVInst16CB<0b100, 0b01, (outs), (ins uimm5slist:$slist), OpcodeStr, "$slist"> {
396+
bits<3> slist;
397+
398+
let Inst{6-2} = 0;
399+
let Inst{9-7} = slist;
400+
let Inst{12-10} = imm5_func2;
401+
}
402+
367403
class QCIRVInstEIBase<bits<3> funct3, bits<2> funct2, dag outs,
368404
dag ins, string opcodestr, string argstr>
369405
: RVInst48<outs, ins, opcodestr, argstr, [], InstFormatOther> {
@@ -744,6 +780,26 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
744780
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
745781
} // Predicates = [HasVendorXqcilia, IsRV32]
746782

783+
let Predicates = [HasVendorXqcisync, IsRV32] in {
784+
def QC_SYNC : QCISync_UIMM5<0b0001, "qc.sync">;
785+
def QC_SYNCR : QCISync_UIMM5<0b0010, "qc.syncr">;
786+
def QC_SYNCWF : QCISync_UIMM5<0b0100, "qc.syncwf">;
787+
def QC_SYNCWL : QCISync_UIMM5<0b1000, "qc.syncwl">;
788+
789+
def QC_C_SYNC : QCIRVInst16CBSYNC<0b000, "qc.c.sync">;
790+
def QC_C_SYNCR : QCIRVInst16CBSYNC<0b001, "qc.c.syncr">;
791+
def QC_C_SYNCWF : QCIRVInst16CBSYNC<0b100, "qc.c.syncwf">;
792+
def QC_C_SYNCWL : QCIRVInst16CBSYNC<0b101, "qc.c.syncwl">;
793+
794+
def QC_C_DELAY : RVInst16CI<0b000, 0b10, (outs),
795+
(ins uimm5nonzero:$imm),
796+
"qc.c.delay", "$imm"> {
797+
let Inst{12} = 0;
798+
let Inst{11-7} = 0;
799+
let Inst{6-2} = imm{4-0};
800+
}
801+
} // Predicates = [HasVendorXqcisync, IsRV32]
802+
747803
let Predicates = [HasVendorXqcisim, IsRV32] in {
748804
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
749805
def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm10:$imm10),

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -744,10 +744,10 @@ Error RISCVISAInfo::checkDependency() {
744744
bool HasXqccmp = Exts.count("xqccmp") != 0;
745745

746746
static constexpr StringLiteral XqciExts[] = {
747-
{"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"},
748-
{"xqcicli"}, {"xqcicm"}, {"xqcics"}, {"xqcicsr"},
749-
{"xqciint"}, {"xqcilb"}, {"xqcili"}, {"xqcilia"},
750-
{"xqcilo"}, {"xqcilsm"}, {"xqcisim"}, {"xqcisls"}};
747+
{"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"}, {"xqcicli"},
748+
{"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilb"},
749+
{"xqcili"}, {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisim"},
750+
{"xqcisls"}, {"xqcisync"}};
751751
static constexpr StringLiteral ZcdOverlaps[] = {
752752
{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
753753

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