@@ -68,7 +68,7 @@ class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
6868}
6969
7070// op vd, vs2, imm
71- class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5 >
71+ class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
7272 : VALUVINoVm<funct6, opcodestr, optype> {
7373 let Inst{6-0} = OPC_OP_P.Value;
7474 let Inst{14-12} = OPMVV.Value;
@@ -85,14 +85,6 @@ multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
8585 def NAME # _VV : PALUVs2NoVm<funct6_vv, vs1, opv, opcodestr # ".vv">;
8686 def NAME # _VS : PALUVs2NoVm<funct6_vs, vs1, opv, opcodestr # ".vs">;
8787}
88-
89- // vaeskf1.vi and vaeskf2.vi uses different opcode and format, we need
90- // to customize one for them.
91- class VAESKF_MV_I<bits<6> funct6, string opcodestr, Operand optype>
92- : VALUVINoVm<funct6, opcodestr, optype> {
93- let Inst{6-0} = OPC_OP_P.Value;
94- let Inst{14-12} = OPMVV.Value;
95- }
9688} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
9789
9890//===----------------------------------------------------------------------===//
@@ -137,8 +129,8 @@ let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
137129 defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
138130 defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
139131 defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
140- def VAESKF1_VI : VAESKF_MV_I <0b100010, "vaeskf1.vi", uimm5>;
141- def VAESKF2_VI : VAESKF_MV_I <0b101010, "vaeskf2.vi", uimm5>;
132+ def VAESKF1_VI : PALUVINoVm <0b100010, "vaeskf1.vi", uimm5>;
133+ def VAESKF2_VI : PALUVINoVm <0b101010, "vaeskf2.vi", uimm5>;
142134 def VAESZ_VS : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
143135} // Predicates = [HasStdExtZvkned]
144136
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