[AArch64] Remove FEAT_TME assembly and ACLE support (#167687)

The Transactional Memory Extension (TME) was introduced as part of
Armv9-A but has not been adopted by the ecosystem. This mirrors what
Arm has observed with similar extensions in other architectures.

Therefore, remove FEAT_TME assembly and ACLE code from llvm, because
support for TME has now been officially withdrawn, as noted here:

```
   FEAT_TME is withdrawn from all future versions of Arm®
   Architecture Reference Manual for A-profile architecture.
```

referenced in Known Issue D24093, documented here:
   https://developer.arm.com/documentation/102105/lb-05/

Author: jthackray

clang/include/clang/Basic/BuiltinsAArch64.def

@@ -109,12 +109,6 @@ BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 // Misc
 BUILTIN(__builtin_sponentry, "v*", "c")
 
-// Transactional Memory Extension
-BUILTIN(__builtin_arm_tstart, "WUi", "nj")
-BUILTIN(__builtin_arm_tcommit, "v", "n")
-BUILTIN(__builtin_arm_tcancel, "vWUIi", "n")
-BUILTIN(__builtin_arm_ttest, "WUi", "nc")
-
 // Armv8.5-A FP rounding intrinsics
 TARGET_BUILTIN(__builtin_arm_rint32zf, "ff", "", "v8.5a")
 TARGET_BUILTIN(__builtin_arm_rint32z, "dd", "", "v8.5a")

clang/lib/Basic/Targets/AArch64.cpp

@@ -606,9 +606,6 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasMTE)
     Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
 
-  if (HasTME)
-    Builder.defineMacro("__ARM_FEATURE_TME", "1");
-
   if (HasMatMul)
     Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
 
@@ -1173,8 +1170,6 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
     }
     if (Feature == "+mte")
       HasMTE = true;
-    if (Feature == "+tme")
-      HasTME = true;
     if (Feature == "+pauth")
       HasPAuth = true;
     if (Feature == "+i8mm")

clang/lib/Basic/Targets/AArch64.h

@@ -75,7 +75,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
   bool HasDotProd = false;
   bool HasFP16FML = false;
   bool HasMTE = false;
-  bool HasTME = false;
   bool HasPAuth = false;
   bool HasLS64 = false;
   bool HasRandGen = false;

clang/lib/Headers/arm_acle.h

@@ -821,28 +821,6 @@ __arm_st64bv0(void *__addr, data512_t __value) {
 
 #endif // __ARM_FEATURE_COPROC
 
-/* 17 Transactional Memory Extension (TME) Intrinsics */
-#if defined(__ARM_FEATURE_TME) && __ARM_FEATURE_TME
-
-#define _TMFAILURE_REASON  0x00007fffu
-#define _TMFAILURE_RTRY    0x00008000u
-#define _TMFAILURE_CNCL    0x00010000u
-#define _TMFAILURE_MEM     0x00020000u
-#define _TMFAILURE_IMP     0x00040000u
-#define _TMFAILURE_ERR     0x00080000u
-#define _TMFAILURE_SIZE    0x00100000u
-#define _TMFAILURE_NEST    0x00200000u
-#define _TMFAILURE_DBG     0x00400000u
-#define _TMFAILURE_INT     0x00800000u
-#define _TMFAILURE_TRIVIAL 0x01000000u
-
-#define __tstart()        __builtin_arm_tstart()
-#define __tcommit()       __builtin_arm_tcommit()
-#define __tcancel(__arg)  __builtin_arm_tcancel(__arg)
-#define __ttest()         __builtin_arm_ttest()
-
-#endif /* __ARM_FEATURE_TME */
-
 /* 8.7 Armv8.5-A Random number generation intrinsics */
 #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
 static __inline__ int __attribute__((__always_inline__, __nodebug__, target("rand")))

clang/lib/Sema/SemaARM.cpp

@@ -1183,7 +1183,6 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI,
     l = 0;
     u = 15;
     break;
-  case AArch64::BI__builtin_arm_tcancel: l = 0; u = 65535; break;
   }
 
   return SemaRef.BuiltinConstantArgRange(TheCall, i, l, u + l);

clang/test/CodeGen/AArch64/tme.cpp

@@ -119,5 +119,4 @@
 // CHECK-NEXT:     the                 FEAT_THE                                               Enable Armv8.9-A Translation Hardening Extension
 // CHECK-NEXT:     tlbid               FEAT_TLBID                                             Enable Armv9.7-A TLBI Domains extension
 // CHECK-NEXT:     tlbiw               FEAT_TLBIW                                             Enable Armv9.5-A TLBI VMALL for Dirty State
-// CHECK-NEXT:     tme                 FEAT_TME                                               Enable Transactional Memory Extension
 // CHECK-NEXT:     wfxt                FEAT_WFxT                                              Enable Armv8.7-A WFET and WFIT instruction

clang/test/Driver/print-supported-extensions-aarch64.c

@@ -61,7 +61,6 @@ fn:
   sm4e z0.s, z0.s, z0.s                 // AEK_SVE2SM4
   addqv   v0.8h, p0, z0.h               // AEK_SVE2P1 / AEK_SME2P1
   rcwswp x0, x1, [x2]                   // AEK_THE
-  tcommit                               // AEK_TME
 lbl:
 .fn_end:
   .size   fn, .fn_end-fn
@@ -81,7 +80,7 @@ lbl:
 # CHECK-NEXT: fcvt   d0, s0
 # CHECK-NEXT: fabs   h1, h2
 # CHECK-NEXT: fmlal  v0.2s, v1.2h, v2.2h
-# CHECK-NEXT: bc.eq 0xc8
+# CHECK-NEXT: bc.eq 0xc4
 # CHECK-NEXT: smmla  v1.4s, v16.16b, v31.16b
 # CHECK-NEXT: ld64b  x0, [x13]
 # CHECK-NEXT: ldaddab w0, w0, [sp]
@@ -116,4 +115,3 @@ lbl:
 # CHECK-NEXT: sm4e   z0.s, z0.s, z0.s
 # CHECK-NEXT: addqv  v0.8h, p0, z0.h
 # CHECK-NEXT: rcwswp x0, x1, [x2]
-# CHECK-NEXT: tcommit