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Minor changes for code quality and clarity
1 parent 9430fcd commit 8ce2dd1

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3 files changed

+2
-6
lines changed

3 files changed

+2
-6
lines changed

llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2999,9 +2999,7 @@ class MaskedHistogramSDNode : public MaskedGatherScatterSDNode {
29992999
EVT MemVT, MachineMemOperand *MMO,
30003000
ISD::MemIndexType IndexType)
30013001
: MaskedGatherScatterSDNode(ISD::EXPERIMENTAL_VECTOR_HISTOGRAM, Order, DL,
3002-
VTs, MemVT, MMO, IndexType) {
3003-
LSBaseSDNodeBits.AddressingMode = IndexType;
3004-
}
3002+
VTs, MemVT, MMO, IndexType) {}
30053003

30063004
ISD::MemIndexType getIndexType() const {
30073005
return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12378,7 +12378,6 @@ SDValue DAGCombiner::visitMHISTOGRAM(SDNode *N) {
1237812378
MMO, IndexType);
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}
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EVT DataVT = Index.getValueType();
12381-
DataVT.changeVectorElementType(Inc.getValueType());
1238212381
if (refineIndexType(Index, IndexType, DataVT, DAG)) {
1238312382
return DAG.getMaskedHistogram(DAG.getVTList(MVT::Other), MemVT, DL, Ops,
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MMO, IndexType);

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24092,9 +24092,8 @@ static SDValue performMaskedGatherScatterCombine(
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SDValue BasePtr = MGS->getBasePtr();
2409324093
ISD::MemIndexType IndexType = MGS->getIndexType();
2409424094

24095-
if (!findMoreOptimalIndexType(MGS, BasePtr, Index, DAG)) {
24095+
if (!findMoreOptimalIndexType(MGS, BasePtr, Index, DAG))
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return SDValue();
24097-
}
2409824097

2409924098
// Here we catch such cases early and change MGATHER's IndexType to allow
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// the use of an Index that's more legalisation friendly.

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