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GrumpyPigSkinGrumpyPigSkin
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Updated failing tests
1 parent e5f7304 commit 8d01cbe

25 files changed

+11550
-7691
lines changed

‎llvm/test/CodeGen/AArch64/bitcast.ll‎

Lines changed: 13 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -49,12 +49,15 @@ define <4 x i16> @foo2(<2 x i32> %a) {
4949
define i32 @bitcast_v4i8_i32(<4 x i8> %a, <4 x i8> %b){
5050
; CHECK-SD-LABEL: bitcast_v4i8_i32:
5151
; CHECK-SD: // %bb.0:
52-
; CHECK-SD-NEXT: sub sp, sp, #16
53-
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
54-
; CHECK-SD-NEXT: add v0.4h, v0.4h, v1.4h
55-
; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b
56-
; CHECK-SD-NEXT: fmov w0, s0
57-
; CHECK-SD-NEXT: add sp, sp, #16
52+
; CHECK-SD-NEXT: add v0.4h, v0.4h, v1.4h
53+
; CHECK-SD-NEXT: umov w8, v0.h[0]
54+
; CHECK-SD-NEXT: umov w9, v0.h[1]
55+
; CHECK-SD-NEXT: umov w10, v0.h[2]
56+
; CHECK-SD-NEXT: and w8, w8, #0xff
57+
; CHECK-SD-NEXT: bfi w8, w9, #8, #8
58+
; CHECK-SD-NEXT: umov w9, v0.h[3]
59+
; CHECK-SD-NEXT: bfi w8, w10, #16, #8
60+
; CHECK-SD-NEXT: orr w0, w8, w9, lsl #24
5861
; CHECK-SD-NEXT: ret
5962
;
6063
; CHECK-GI-LABEL: bitcast_v4i8_i32:
@@ -99,15 +102,10 @@ define <4 x i8> @bitcast_i32_v4i8(i32 %a, i32 %b){
99102
define i32 @bitcast_v2i16_i32(<2 x i16> %a, <2 x i16> %b){
100103
; CHECK-SD-LABEL: bitcast_v2i16_i32:
101104
; CHECK-SD: // %bb.0:
102-
; CHECK-SD-NEXT: sub sp, sp, #16
103-
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
104-
; CHECK-SD-NEXT: add v0.2s, v0.2s, v1.2s
105-
; CHECK-SD-NEXT: mov w8, v0.s[1]
106-
; CHECK-SD-NEXT: fmov w9, s0
107-
; CHECK-SD-NEXT: strh w9, [sp, #12]
108-
; CHECK-SD-NEXT: strh w8, [sp, #14]
109-
; CHECK-SD-NEXT: ldr w0, [sp, #12]
110-
; CHECK-SD-NEXT: add sp, sp, #16
105+
; CHECK-SD-NEXT: add v0.2s, v0.2s, v1.2s
106+
; CHECK-SD-NEXT: mov w8, v0.s[1]
107+
; CHECK-SD-NEXT: fmov w0, s0
108+
; CHECK-SD-NEXT: bfi w0, w8, #16, #16
111109
; CHECK-SD-NEXT: ret
112110
;
113111
; CHECK-GI-LABEL: bitcast_v2i16_i32:

‎llvm/test/CodeGen/AArch64/shufflevector.ll‎

Lines changed: 25 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -229,15 +229,17 @@ define <2 x i1> @shufflevector_v2i1(<2 x i1> %a, <2 x i1> %b){
229229
define i32 @shufflevector_v4i8(<4 x i8> %a, <4 x i8> %b){
230230
; CHECK-SD-LABEL: shufflevector_v4i8:
231231
; CHECK-SD: // %bb.0:
232-
; CHECK-SD-NEXT: sub sp, sp, #16
233-
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
234-
; CHECK-SD-NEXT: ext v0.8b, v1.8b, v0.8b, #6
235-
; CHECK-SD-NEXT: zip1 v1.4h, v1.4h, v0.4h
236-
; CHECK-SD-NEXT: ext v0.8b, v0.8b, v1.8b, #4
237-
; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b
238-
; CHECK-SD-NEXT: fmov w0, s0
239-
; CHECK-SD-NEXT: add sp, sp, #16
240-
; CHECK-SD-NEXT: ret
232+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
233+
; CHECK-SD-NEXT: umov w8, v0.h[1]
234+
; CHECK-SD-NEXT: umov w9, v0.h[2]
235+
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
236+
; CHECK-SD-NEXT: umov w10, v1.h[0]
237+
; CHECK-SD-NEXT: and w8, w8, #0xff
238+
; CHECK-SD-NEXT: bfi w8, w9, #8, #8
239+
; CHECK-SD-NEXT: umov w9, v1.h[3]
240+
; CHECK-SD-NEXT: bfi w8, w10, #16, #8
241+
; CHECK-SD-NEXT: orr w0, w8, w9, lsl #24
242+
; CHECK-SD-NEXT: ret
241243
;
242244
; CHECK-GI-LABEL: shufflevector_v4i8:
243245
; CHECK-GI: // %bb.0:
@@ -285,15 +287,11 @@ define <32 x i8> @shufflevector_v32i8(<32 x i8> %a, <32 x i8> %b){
285287
define i32 @shufflevector_v2i16(<2 x i16> %a, <2 x i16> %b){
286288
; CHECK-SD-LABEL: shufflevector_v2i16:
287289
; CHECK-SD: // %bb.0:
288-
; CHECK-SD-NEXT: sub sp, sp, #16
289-
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
290-
; CHECK-SD-NEXT: ext v0.8b, v0.8b, v1.8b, #4
291-
; CHECK-SD-NEXT: mov w8, v0.s[1]
292-
; CHECK-SD-NEXT: fmov w9, s0
293-
; CHECK-SD-NEXT: strh w9, [sp, #12]
294-
; CHECK-SD-NEXT: strh w8, [sp, #14]
295-
; CHECK-SD-NEXT: ldr w0, [sp, #12]
296-
; CHECK-SD-NEXT: add sp, sp, #16
290+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
291+
; CHECK-SD-NEXT: mov w0, v0.s[1]
292+
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
293+
; CHECK-SD-NEXT: fmov w8, s1
294+
; CHECK-SD-NEXT: bfi w0, w8, #16, #16
297295
; CHECK-SD-NEXT: ret
298296
;
299297
; CHECK-GI-LABEL: shufflevector_v2i16:
@@ -462,14 +460,13 @@ define <2 x i1> @shufflevector_v2i1_zeroes(<2 x i1> %a, <2 x i1> %b){
462460
define i32 @shufflevector_v4i8_zeroes(<4 x i8> %a, <4 x i8> %b){
463461
; CHECK-SD-LABEL: shufflevector_v4i8_zeroes:
464462
; CHECK-SD: // %bb.0:
465-
; CHECK-SD-NEXT: sub sp, sp, #16
466-
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
467-
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
468-
; CHECK-SD-NEXT: dup v0.4h, v0.h[0]
469-
; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b
470-
; CHECK-SD-NEXT: fmov w0, s0
471-
; CHECK-SD-NEXT: add sp, sp, #16
472-
; CHECK-SD-NEXT: ret
463+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
464+
; CHECK-SD-NEXT: umov w8, v0.h[0]
465+
; CHECK-SD-NEXT: and w9, w8, #0xff
466+
; CHECK-SD-NEXT: orr w9, w9, w9, lsl #8
467+
; CHECK-SD-NEXT: bfi w9, w8, #16, #8
468+
; CHECK-SD-NEXT: orr w0, w9, w8, lsl #24
469+
; CHECK-SD-NEXT: ret
473470
;
474471
; CHECK-GI-LABEL: shufflevector_v4i8_zeroes:
475472
; CHECK-GI: // %bb.0:
@@ -495,16 +492,9 @@ define <32 x i8> @shufflevector_v32i8_zeroes(<32 x i8> %a, <32 x i8> %b){
495492
define i32 @shufflevector_v2i16_zeroes(<2 x i16> %a, <2 x i16> %b){
496493
; CHECK-SD-LABEL: shufflevector_v2i16_zeroes:
497494
; CHECK-SD: // %bb.0:
498-
; CHECK-SD-NEXT: sub sp, sp, #16
499-
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
500495
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
501-
; CHECK-SD-NEXT: dup v1.2s, v0.s[0]
502-
; CHECK-SD-NEXT: fmov w9, s0
503-
; CHECK-SD-NEXT: strh w9, [sp, #12]
504-
; CHECK-SD-NEXT: mov w8, v1.s[1]
505-
; CHECK-SD-NEXT: strh w8, [sp, #14]
506-
; CHECK-SD-NEXT: ldr w0, [sp, #12]
507-
; CHECK-SD-NEXT: add sp, sp, #16
496+
; CHECK-SD-NEXT: fmov w0, s0
497+
; CHECK-SD-NEXT: bfi w0, w0, #16, #16
508498
; CHECK-SD-NEXT: ret
509499
;
510500
; CHECK-GI-LABEL: shufflevector_v2i16_zeroes:

‎llvm/test/CodeGen/AMDGPU/build_vector-r600.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -45,12 +45,12 @@ define amdgpu_kernel void @build_vector_v2i16 (ptr addrspace(1) %out) {
4545
; R600-LABEL: build_vector_v2i16:
4646
; R600: ; %bb.0: ; %entry
4747
; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
48-
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 1
48+
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
4949
; R600-NEXT: CF_END
5050
; R600-NEXT: PAD
5151
; R600-NEXT: ALU clause starting at 4:
52-
; R600-NEXT: MOV T4.X, literal.x,
53-
; R600-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
52+
; R600-NEXT: MOV T0.X, literal.x,
53+
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
5454
; R600-NEXT: 393221(5.510200e-40), 2(2.802597e-45)
5555
entry:
5656
store <2 x i16> <i16 5, i16 6>, ptr addrspace(1) %out
@@ -61,14 +61,14 @@ define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32
6161
; R600-LABEL: build_vector_v2i16_trunc:
6262
; R600: ; %bb.0:
6363
; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
64-
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 1
64+
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
6565
; R600-NEXT: CF_END
6666
; R600-NEXT: PAD
6767
; R600-NEXT: ALU clause starting at 4:
68-
; R600-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,
68+
; R600-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,
6969
; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
70-
; R600-NEXT: OR_INT T4.X, PV.W, literal.x,
71-
; R600-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
70+
; R600-NEXT: OR_INT T0.X, PV.W, literal.x,
71+
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
7272
; R600-NEXT: 327680(4.591775e-40), 2(2.802597e-45)
7373
%srl = lshr i32 %a, 16
7474
%trunc = trunc i32 %srl to i16

‎llvm/test/CodeGen/AMDGPU/ctpop16.ll‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -368,26 +368,26 @@ define amdgpu_kernel void @v_ctpop_v2i16(ptr addrspace(1) noalias %out, ptr addr
368368
; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
369369
; EG-NEXT: TEX 0 @6
370370
; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[]
371-
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T6.X, 1
371+
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
372372
; EG-NEXT: CF_END
373373
; EG-NEXT: PAD
374374
; EG-NEXT: Fetch clause starting at 6:
375-
; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
375+
; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
376376
; EG-NEXT: ALU clause starting at 8:
377-
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
377+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
378378
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
379-
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
379+
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
380380
; EG-NEXT: ALU clause starting at 11:
381-
; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
381+
; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
382382
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
383-
; EG-NEXT: BCNT_INT T0.W, PV.W,
384-
; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
383+
; EG-NEXT: BCNT_INT T0.W, PV.W,
384+
; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
385385
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
386-
; EG-NEXT: BCNT_INT T1.W, PS,
387-
; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
386+
; EG-NEXT: BCNT_INT T1.W, PS,
387+
; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
388388
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
389-
; EG-NEXT: OR_INT T0.X, PV.W, PS,
390-
; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,
389+
; EG-NEXT: OR_INT T0.X, PV.W, PS,
390+
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
391391
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
392392
%tid = call i32 @llvm.amdgcn.workitem.id.x()
393393
%in.gep = getelementptr <2 x i16>, ptr addrspace(1) %in, i32 %tid

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