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paulwalker-armpaulwalker-arm
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[LLVM][SVE] Add isel for bfloat based select operations.
Patch also adds missing tests for unpacked half and float types.
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3 files changed

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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1701,6 +1701,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FP_ROUND, VT, Custom);
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setOperationAction(ISD::MLOAD, VT, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::SELECT_CC, VT, Expand);
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setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
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setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);
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‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

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Original file line numberDiff line numberDiff line change
@@ -1962,6 +1962,8 @@ multiclass sve_int_sel_vvv<string asm, SDPatternOperator op> {
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def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
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def : SVE_3_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME # _H)>;
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def : SVE_3_Op_Pat<nxv4bf16, op, nxv4i1, nxv4bf16, nxv4bf16, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_Pat<nxv2bf16, op, nxv2i1, nxv2bf16, nxv2bf16, !cast<Instruction>(NAME # _D)>;
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def : InstAlias<"mov $Zd, $Pg/m, $Zn",
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(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>;

‎llvm/test/CodeGen/AArch64/sve-select.ll‎

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,30 @@ define <vscale x 8 x half> @select_nxv8f16(i1 %cond, <vscale x 8 x half> %a, <
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ret <vscale x 8 x half> %res
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}
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define <vscale x 4 x half> @select_nxv4f16(i1 %cond, <vscale x 4 x half> %a, <vscale x 4 x half> %b) {
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; CHECK-LABEL: select_nxv4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sbfx x8, x0, #0, #1
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; CHECK-NEXT: whilelo p0.s, xzr, x8
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; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
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; CHECK-NEXT: ret
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%res = select i1 %cond, <vscale x 4 x half> %a, <vscale x 4 x half> %b
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ret <vscale x 4 x half> %res
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}
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define <vscale x 2 x half> @select_nxv2f16(i1 %cond, <vscale x 2 x half> %a, <vscale x 2 x half> %b) {
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; CHECK-LABEL: select_nxv2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sbfx x8, x0, #0, #1
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; CHECK-NEXT: whilelo p0.d, xzr, x8
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; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = select i1 %cond, <vscale x 2 x half> %a, <vscale x 2 x half> %b
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ret <vscale x 2 x half> %res
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}
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define <vscale x 4 x float> @select_nxv4f32(i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
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; CHECK-LABEL: select_nxv4f32:
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; CHECK: // %bb.0:
@@ -121,6 +145,18 @@ define <vscale x 4 x float> @select_nxv4f32(i1 %cond, <vscale x 4 x float> %a,
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ret <vscale x 4 x float> %res
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}
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define <vscale x 2 x float> @select_nxv2f32(i1 %cond, <vscale x 2 x float> %a, <vscale x 2 x float> %b) {
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; CHECK-LABEL: select_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sbfx x8, x0, #0, #1
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; CHECK-NEXT: whilelo p0.d, xzr, x8
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; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = select i1 %cond, <vscale x 2 x float> %a, <vscale x 2 x float> %b
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ret <vscale x 2 x float> %res
158+
}
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define <vscale x 2 x double> @select_nxv2f64(i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
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; CHECK-LABEL: select_nxv2f64:
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; CHECK: // %bb.0:
@@ -133,6 +169,42 @@ define <vscale x 2 x double> @select_nxv2f64(i1 %cond, <vscale x 2 x double> %
133169
ret <vscale x 2 x double> %res
134170
}
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define <vscale x 8 x bfloat> @select_nxv8bf16(i1 %cond, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
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; CHECK-LABEL: select_nxv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sbfx x8, x0, #0, #1
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; CHECK-NEXT: whilelo p0.h, xzr, x8
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; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
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; CHECK-NEXT: ret
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%res = select i1 %cond, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b
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ret <vscale x 8 x bfloat> %res
182+
}
183+
184+
define <vscale x 4 x bfloat> @select_nxv4bf16(i1 %cond, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {
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; CHECK-LABEL: select_nxv4bf16:
186+
; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sbfx x8, x0, #0, #1
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; CHECK-NEXT: whilelo p0.s, xzr, x8
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; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
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; CHECK-NEXT: ret
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%res = select i1 %cond, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b
193+
ret <vscale x 4 x bfloat> %res
194+
}
195+
196+
define <vscale x 2 x bfloat> @select_nxv2bf16(i1 %cond, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {
197+
; CHECK-LABEL: select_nxv2bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
200+
; CHECK-NEXT: sbfx x8, x0, #0, #1
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; CHECK-NEXT: whilelo p0.d, xzr, x8
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; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = select i1 %cond, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b
205+
ret <vscale x 2 x bfloat> %res
206+
}
207+
136208
define <vscale x 16 x i1> @select_nxv16i1(i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
137209
; CHECK-LABEL: select_nxv16i1:
138210
; CHECK: // %bb.0:
@@ -324,6 +396,20 @@ define <vscale x 2 x double> @icmp_select_nxv2f64(<vscale x 2 x double> %a, <vsc
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ret <vscale x 2 x double> %sel
325397
}
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399+
define <vscale x 2 x bfloat> @icmp_select_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i64 %x0) {
400+
; CHECK-LABEL: icmp_select_nxv2bf16:
401+
; CHECK: // %bb.0:
402+
; CHECK-NEXT: cmp x0, #0
403+
; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: sbfx x8, x8, #0, #1
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; CHECK-NEXT: whilelo p0.d, xzr, x8
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; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
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; CHECK-NEXT: ret
408+
%mask = icmp eq i64 %x0, 0
409+
%sel = select i1 %mask, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b
410+
ret <vscale x 2 x bfloat> %sel
411+
}
412+
327413
define <vscale x 4 x half> @icmp_select_nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i64 %x0) {
328414
; CHECK-LABEL: icmp_select_nxv4f16:
329415
; CHECK: // %bb.0:
@@ -352,6 +438,20 @@ define <vscale x 4 x float> @icmp_select_nxv4f32(<vscale x 4 x float> %a, <vscal
352438
ret <vscale x 4 x float> %sel
353439
}
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441+
define <vscale x 4 x bfloat> @icmp_select_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i64 %x0) {
442+
; CHECK-LABEL: icmp_select_nxv4bf16:
443+
; CHECK: // %bb.0:
444+
; CHECK-NEXT: cmp x0, #0
445+
; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: sbfx x8, x8, #0, #1
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; CHECK-NEXT: whilelo p0.s, xzr, x8
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; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
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; CHECK-NEXT: ret
450+
%mask = icmp eq i64 %x0, 0
451+
%sel = select i1 %mask, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b
452+
ret <vscale x 4 x bfloat> %sel
453+
}
454+
355455
define <vscale x 8 x half> @icmp_select_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i64 %x0) {
356456
; CHECK-LABEL: icmp_select_nxv8f16:
357457
; CHECK: // %bb.0:
@@ -366,6 +466,20 @@ define <vscale x 8 x half> @icmp_select_nxv8f16(<vscale x 8 x half> %a, <vscale
366466
ret <vscale x 8 x half> %sel
367467
}
368468

469+
define <vscale x 8 x bfloat> @icmp_select_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i64 %x0) {
470+
; CHECK-LABEL: icmp_select_nxv8bf16:
471+
; CHECK: // %bb.0:
472+
; CHECK-NEXT: cmp x0, #0
473+
; CHECK-NEXT: cset w8, eq
474+
; CHECK-NEXT: sbfx x8, x8, #0, #1
475+
; CHECK-NEXT: whilelo p0.h, xzr, x8
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; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
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; CHECK-NEXT: ret
478+
%mask = icmp eq i64 %x0, 0
479+
%sel = select i1 %mask, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b
480+
ret <vscale x 8 x bfloat> %sel
481+
}
482+
369483
define <vscale x 1 x i64> @icmp_select_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i64 %x0) {
370484
; CHECK-LABEL: icmp_select_nxv1i64:
371485
; CHECK: // %bb.0:

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