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[AMDGPU][GlobalISel] Combine (or s64, zext(s32))
1 parent 4ecb646 commit 8d4669a

15 files changed

+617
-837
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUCombine.td‎

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,19 @@ def binop_s64_with_s32_mask_combines : GICombineGroup<[
176176
combine_or_s64_with_s32_mask, combine_and_s64_with_s32_mask
177177
]>;
178178

179+
// (or i64:x, (zext i32:y)) -> i64:(merge (or lo_32(x), i32:y), hi_32(x))
180+
// (or (zext i32:y), i64:x) -> i64:(merge (or lo_32(x), i32:y), hi_32(x))
181+
def or_s64_zext_s32_frag : GICombinePatFrag<(outs root:$dst), (ins $src_s64, $src_s32),
182+
[(pattern (G_OR $dst, i64:$src_s64, i64:$zext_val), (G_ZEXT i64:$zext_val, i32:$src_s32)),
183+
(pattern (G_OR $dst, i64:$zext_val, i64:$src_s64), (G_ZEXT i64:$zext_val, i32:$src_s32))]>;
184+
185+
def combine_or_s64_s32 : GICombineRule<
186+
(defs root:$dst),
187+
(match (or_s64_zext_s32_frag $dst, i64:$x, i32:$y):$dst),
188+
(apply (G_UNMERGE_VALUES $x_lo, $x_hi, $x),
189+
(G_OR $or, $x_lo, $y),
190+
(G_MERGE_VALUES $dst, $or, $x_hi))>;
191+
179192
let Predicates = [Has16BitInsts, NotHasMed3_16] in {
180193
// For gfx8, expand f16-fmed3-as-f32 into a min/max f16 sequence. This
181194
// saves one instruction compared to the promotion.
@@ -206,7 +219,7 @@ def AMDGPUPreLegalizerCombiner: GICombiner<
206219
"AMDGPUPreLegalizerCombinerImpl",
207220
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
208221
foldable_fneg, combine_shuffle_vector_to_build_vector,
209-
binop_s64_with_s32_mask_combines]> {
222+
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
210223
let CombineAllMethodName = "tryCombineAllImpl";
211224
}
212225

@@ -215,7 +228,7 @@ def AMDGPUPostLegalizerCombiner: GICombiner<
215228
[all_combines, gfx6gfx7_combines, gfx8_combines, combine_fmul_with_select_to_fldexp,
216229
uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
217230
rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64,
218-
binop_s64_with_s32_mask_combines]> {
231+
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
219232
let CombineAllMethodName = "tryCombineAllImpl";
220233
}
221234

‎llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1778,7 +1778,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
17781778
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v1
17791779
; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], 31
17801780
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v3
1781-
; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
1781+
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
17821782
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 1, v2
17831783
; GFX6-NEXT: s_setpc_b64 s[30:31]
17841784
;
@@ -1790,7 +1790,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
17901790
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
17911791
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
17921792
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v3
1793-
; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
1793+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
17941794
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 1, v2
17951795
; GFX8-NEXT: s_setpc_b64 s[30:31]
17961796
;
@@ -1802,7 +1802,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
18021802
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
18031803
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
18041804
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
1805-
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
1805+
; GFX9-NEXT: v_or_b32_e32 v0, v0, v3
18061806
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2
18071807
; GFX9-NEXT: s_setpc_b64 s[30:31]
18081808
;
@@ -1815,7 +1815,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
18151815
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v1
18161816
; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
18171817
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v2
1818-
; GFX10PLUS-NEXT: v_or_b32_e32 v0, v3, v0
1818+
; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v3
18191819
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
18201820
%result = ashr i65 %value, 33
18211821
ret i65 %result
@@ -1875,21 +1875,19 @@ define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
18751875
; GCN-LABEL: s_ashr_i65_33:
18761876
; GCN: ; %bb.0:
18771877
; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
1878-
; GCN-NEXT: s_lshr_b32 s0, s1, 1
1879-
; GCN-NEXT: s_mov_b32 s1, 0
1880-
; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
1881-
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
1878+
; GCN-NEXT: s_lshr_b32 s4, s1, 1
1879+
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
1880+
; GCN-NEXT: s_or_b32 s0, s0, s4
18821881
; GCN-NEXT: s_ashr_i32 s2, s3, 1
18831882
; GCN-NEXT: ; return to shader part epilog
18841883
;
18851884
; GFX10PLUS-LABEL: s_ashr_i65_33:
18861885
; GFX10PLUS: ; %bb.0:
18871886
; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
1888-
; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 1
1889-
; GFX10PLUS-NEXT: s_mov_b32 s1, 0
1890-
; GFX10PLUS-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
1887+
; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 1
1888+
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
18911889
; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 1
1892-
; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
1890+
; GFX10PLUS-NEXT: s_or_b32 s0, s0, s4
18931891
; GFX10PLUS-NEXT: ; return to shader part epilog
18941892
%result = ashr i65 %value, 33
18951893
ret i65 %result

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir‎

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,10 @@ body: |
1212
; CHECK-NEXT: {{ $}}
1313
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
1414
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
15-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
16-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[ZEXT]]
17-
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[OR]](s64)
15+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
16+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[COPY1]]
17+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[UV1]](s32)
18+
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[MV]](s64)
1819
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
1920
%0:_(s64) = COPY $sgpr0_sgpr1
2021
%1:_(s32) = COPY $sgpr2
@@ -34,9 +35,10 @@ body: |
3435
; CHECK-NEXT: {{ $}}
3536
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
3637
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
37-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
38-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[COPY]]
39-
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[OR]](s64)
38+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
39+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[COPY1]]
40+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[UV1]](s32)
41+
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[MV]](s64)
4042
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
4143
%0:_(s64) = COPY $sgpr0_sgpr1
4244
%1:_(s32) = COPY $sgpr2
@@ -57,12 +59,9 @@ body: |
5759
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
5860
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
5961
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2
60-
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
61-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
62-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[MV]], [[ZEXT]]
63-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
64-
; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32)
65-
; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32)
62+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY2]]
63+
; CHECK-NEXT: $sgpr0 = COPY [[OR]](s32)
64+
; CHECK-NEXT: $sgpr1 = COPY [[COPY1]](s32)
6665
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
6766
%0:_(s32) = COPY $sgpr0
6867
%1:_(s32) = COPY $sgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -227,39 +227,38 @@ exit:
227227
define amdgpu_cs void @single_lane_execution_attribute(i32 inreg %.userdata0, <3 x i32> inreg %.WorkgroupId, <3 x i32> %.LocalInvocationId) #0 {
228228
; GFX10-LABEL: single_lane_execution_attribute:
229229
; GFX10: ; %bb.0: ; %.entry
230-
; GFX10-NEXT: s_getpc_b64 s[12:13]
231-
; GFX10-NEXT: s_mov_b32 s12, 0
230+
; GFX10-NEXT: s_getpc_b64 s[4:5]
232231
; GFX10-NEXT: s_mov_b32 s2, s0
233-
; GFX10-NEXT: s_mov_b32 s3, s12
232+
; GFX10-NEXT: s_mov_b32 s3, s5
234233
; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, -1, 0
235-
; GFX10-NEXT: s_or_b64 s[2:3], s[12:13], s[2:3]
236234
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
237235
; GFX10-NEXT: v_mbcnt_hi_u32_b32 v1, -1, v1
238236
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v1
239237
; GFX10-NEXT: v_and_b32_e32 v3, 1, v1
240238
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
241239
; GFX10-NEXT: s_xor_b32 s2, vcc_lo, exec_lo
242-
; GFX10-NEXT: s_and_b32 vcc_lo, s2, exec_lo
243240
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
244241
; GFX10-NEXT: buffer_load_dword v2, v2, s[4:7], 0 offen
242+
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
243+
; GFX10-NEXT: s_mov_b32 s2, 0
245244
; GFX10-NEXT: s_waitcnt vmcnt(0)
246245
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v2
247246
; GFX10-NEXT: s_cbranch_vccnz .LBB4_4
248247
; GFX10-NEXT: ; %bb.1: ; %.preheader.preheader
249-
; GFX10-NEXT: s_mov_b32 s2, 0
248+
; GFX10-NEXT: s_mov_b32 s3, 0
250249
; GFX10-NEXT: .LBB4_2: ; %.preheader
251250
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
252-
; GFX10-NEXT: v_mov_b32_e32 v3, s12
251+
; GFX10-NEXT: v_mov_b32_e32 v3, s2
253252
; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1
254-
; GFX10-NEXT: s_add_i32 s12, s12, 4
253+
; GFX10-NEXT: s_add_i32 s2, s2, 4
255254
; GFX10-NEXT: buffer_load_dword v3, v3, s[4:7], 0 offen
256255
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
257256
; GFX10-NEXT: s_waitcnt vmcnt(0)
258-
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
259-
; GFX10-NEXT: s_add_i32 s2, s3, s2
257+
; GFX10-NEXT: v_readfirstlane_b32 s12, v3
258+
; GFX10-NEXT: s_add_i32 s3, s12, s3
260259
; GFX10-NEXT: s_cbranch_vccnz .LBB4_2
261260
; GFX10-NEXT: ; %bb.3: ; %.preheader._crit_edge
262-
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s2, v2
261+
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s3, v2
263262
; GFX10-NEXT: s_or_b32 s2, s0, vcc_lo
264263
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
265264
; GFX10-NEXT: s_branch .LBB4_6

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll‎

Lines changed: 27 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -4934,17 +4934,15 @@ define amdgpu_ps i64 @s_fshl_i64_5(i64 inreg %lhs, i64 inreg %rhs) {
49344934
; GCN: ; %bb.0:
49354935
; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 5
49364936
; GCN-NEXT: s_lshr_b32 s2, s3, 27
4937-
; GCN-NEXT: s_mov_b32 s3, 0
4938-
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
4937+
; GCN-NEXT: s_or_b32 s0, s0, s2
49394938
; GCN-NEXT: ; return to shader part epilog
49404939
;
49414940
; GFX11-LABEL: s_fshl_i64_5:
49424941
; GFX11: ; %bb.0:
49434942
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 5
49444943
; GFX11-NEXT: s_lshr_b32 s2, s3, 27
4945-
; GFX11-NEXT: s_mov_b32 s3, 0
49464944
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
4947-
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
4945+
; GFX11-NEXT: s_or_b32 s0, s0, s2
49484946
; GFX11-NEXT: ; return to shader part epilog
49494947
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 5)
49504948
ret i64 %result
@@ -4954,20 +4952,13 @@ define amdgpu_ps i64 @s_fshl_i64_32(i64 inreg %lhs, i64 inreg %rhs) {
49544952
; GCN-LABEL: s_fshl_i64_32:
49554953
; GCN: ; %bb.0:
49564954
; GCN-NEXT: s_mov_b32 s1, s0
4957-
; GCN-NEXT: s_mov_b32 s0, 0
4958-
; GCN-NEXT: s_mov_b32 s2, s3
4959-
; GCN-NEXT: s_mov_b32 s3, s0
4960-
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
4955+
; GCN-NEXT: s_mov_b32 s0, s3
49614956
; GCN-NEXT: ; return to shader part epilog
49624957
;
49634958
; GFX11-LABEL: s_fshl_i64_32:
49644959
; GFX11: ; %bb.0:
49654960
; GFX11-NEXT: s_mov_b32 s1, s0
4966-
; GFX11-NEXT: s_mov_b32 s0, 0
4967-
; GFX11-NEXT: s_mov_b32 s2, s3
4968-
; GFX11-NEXT: s_mov_b32 s3, s0
4969-
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
4970-
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
4961+
; GFX11-NEXT: s_mov_b32 s0, s3
49714962
; GFX11-NEXT: ; return to shader part epilog
49724963
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 32)
49734964
ret i64 %result
@@ -6823,56 +6814,50 @@ define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
68236814
; GFX6: ; %bb.0:
68246815
; GFX6-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
68256816
; GFX6-NEXT: s_lshr_b32 s4, s5, 31
6826-
; GFX6-NEXT: s_mov_b32 s5, 0
68276817
; GFX6-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6828-
; GFX6-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
6818+
; GFX6-NEXT: s_or_b32 s0, s0, s4
68296819
; GFX6-NEXT: s_lshr_b32 s4, s7, 31
6830-
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
6820+
; GFX6-NEXT: s_or_b32 s2, s2, s4
68316821
; GFX6-NEXT: ; return to shader part epilog
68326822
;
68336823
; GFX8-LABEL: s_fshl_i128_65:
68346824
; GFX8: ; %bb.0:
68356825
; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
68366826
; GFX8-NEXT: s_lshr_b32 s4, s5, 31
6837-
; GFX8-NEXT: s_mov_b32 s5, 0
68386827
; GFX8-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6839-
; GFX8-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
6828+
; GFX8-NEXT: s_or_b32 s0, s0, s4
68406829
; GFX8-NEXT: s_lshr_b32 s4, s7, 31
6841-
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
6830+
; GFX8-NEXT: s_or_b32 s2, s2, s4
68426831
; GFX8-NEXT: ; return to shader part epilog
68436832
;
68446833
; GFX9-LABEL: s_fshl_i128_65:
68456834
; GFX9: ; %bb.0:
68466835
; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
68476836
; GFX9-NEXT: s_lshr_b32 s4, s5, 31
6848-
; GFX9-NEXT: s_mov_b32 s5, 0
68496837
; GFX9-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6850-
; GFX9-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
6838+
; GFX9-NEXT: s_or_b32 s0, s0, s4
68516839
; GFX9-NEXT: s_lshr_b32 s4, s7, 31
6852-
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
6840+
; GFX9-NEXT: s_or_b32 s2, s2, s4
68536841
; GFX9-NEXT: ; return to shader part epilog
68546842
;
68556843
; GFX10-LABEL: s_fshl_i128_65:
68566844
; GFX10: ; %bb.0:
6857-
; GFX10-NEXT: s_lshr_b32 s2, s5, 31
6858-
; GFX10-NEXT: s_mov_b32 s3, 0
6859-
; GFX10-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
6860-
; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
6861-
; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
6862-
; GFX10-NEXT: s_lshr_b32 s2, s7, 31
6863-
; GFX10-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
6845+
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
6846+
; GFX10-NEXT: s_lshr_b32 s4, s5, 31
6847+
; GFX10-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6848+
; GFX10-NEXT: s_lshr_b32 s5, s7, 31
6849+
; GFX10-NEXT: s_or_b32 s0, s0, s4
6850+
; GFX10-NEXT: s_or_b32 s2, s2, s5
68646851
; GFX10-NEXT: ; return to shader part epilog
68656852
;
68666853
; GFX11-LABEL: s_fshl_i128_65:
68676854
; GFX11: ; %bb.0:
6868-
; GFX11-NEXT: s_lshr_b32 s2, s5, 31
6869-
; GFX11-NEXT: s_mov_b32 s3, 0
6870-
; GFX11-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
6871-
; GFX11-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
6872-
; GFX11-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
6873-
; GFX11-NEXT: s_lshr_b32 s2, s7, 31
6874-
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
6875-
; GFX11-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
6855+
; GFX11-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
6856+
; GFX11-NEXT: s_lshr_b32 s4, s5, 31
6857+
; GFX11-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6858+
; GFX11-NEXT: s_lshr_b32 s5, s7, 31
6859+
; GFX11-NEXT: s_or_b32 s0, s0, s4
6860+
; GFX11-NEXT: s_or_b32 s2, s2, s5
68766861
; GFX11-NEXT: ; return to shader part epilog
68776862
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)
68786863
ret i128 %result
@@ -6885,7 +6870,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
68856870
; GFX6-NEXT: v_lshl_b64 v[2:3], v[0:1], 1
68866871
; GFX6-NEXT: v_lshl_b64 v[0:1], v[6:7], 1
68876872
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v5
6888-
; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
6873+
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
68896874
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v7
68906875
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
68916876
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -6896,7 +6881,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
68966881
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
68976882
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
68986883
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v5
6899-
; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
6884+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
69006885
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v7
69016886
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
69026887
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -6907,7 +6892,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
69076892
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
69086893
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
69096894
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v5
6910-
; GFX9-NEXT: v_or_b32_e32 v0, v4, v0
6895+
; GFX9-NEXT: v_or_b32_e32 v0, v0, v4
69116896
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v7
69126897
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
69136898
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -6919,7 +6904,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
69196904
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
69206905
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v5
69216906
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 31, v7
6922-
; GFX10-NEXT: v_or_b32_e32 v0, v4, v0
6907+
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
69236908
; GFX10-NEXT: v_or_b32_e32 v2, v2, v5
69246909
; GFX10-NEXT: s_setpc_b64 s[30:31]
69256910
;
@@ -6931,7 +6916,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
69316916
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v5
69326917
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 31, v7
69336918
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
6934-
; GFX11-NEXT: v_or_b32_e32 v0, v4, v0
6919+
; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
69356920
; GFX11-NEXT: v_or_b32_e32 v2, v2, v5
69366921
; GFX11-NEXT: s_setpc_b64 s[30:31]
69376922
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)

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