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[RFC][TableGen] Require DAG argument for complex operands in InstAlias
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12 files changed

+327
-316
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12 files changed

+327
-316
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 59 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -3028,8 +3028,12 @@ class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
30283028

30293029
// Aliases for register+register add/subtract.
30303030
class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
3031-
RegisterClass src1Regtype, RegisterClass src2Regtype,
3032-
int shiftExt>
3031+
RegisterClass src1Regtype, dag src2>
3032+
: InstAlias<asm#"\t$dst, $src1, $src2",
3033+
(inst dstRegtype:$dst, src1Regtype:$src1, src2)>;
3034+
class AddSubRegAlias64<string asm, Instruction inst, RegisterClass dstRegtype,
3035+
RegisterClass src1Regtype, RegisterClass src2Regtype,
3036+
int shiftExt>
30333037
: InstAlias<asm#"\t$dst, $src1, $src2",
30343038
(inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
30353039
shiftExt)>;
@@ -3097,22 +3101,22 @@ multiclass AddSub<bit isSub, string mnemonic, string alias,
30973101

30983102
// Register/register aliases with no shift when SP is not used.
30993103
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
3100-
GPR32, GPR32, GPR32, 0>;
3104+
GPR32, GPR32, (arith_shifted_reg32 GPR32:$src2, 0)>;
31013105
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
3102-
GPR64, GPR64, GPR64, 0>;
3106+
GPR64, GPR64, (arith_shifted_reg64 GPR64:$src2, 0)>;
31033107

31043108
// Register/register aliases with no shift when either the destination or
31053109
// first source register is SP.
31063110
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
3107-
GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
3111+
GPR32sponly, GPR32sp,
3112+
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
31083113
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
3109-
GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
3110-
def : AddSubRegAlias<mnemonic,
3111-
!cast<Instruction>(NAME#"Xrx64"),
3112-
GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
3113-
def : AddSubRegAlias<mnemonic,
3114-
!cast<Instruction>(NAME#"Xrx64"),
3115-
GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
3114+
GPR32sp, GPR32sponly,
3115+
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
3116+
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
3117+
GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
3118+
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
3119+
GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
31163120
}
31173121

31183122
multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
@@ -3176,15 +3180,19 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
31763180
def : InstAlias<cmp#"\t$src, $imm", (!cast<Instruction>(NAME#"Xri")
31773181
XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
31783182
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
3179-
WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
3183+
WZR, GPR32sp:$src1,
3184+
(arith_extended_reg32_i32 GPR32:$src2, arith_extend:$sh)), 4>;
31803185
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
3181-
XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
3186+
XZR, GPR64sp:$src1,
3187+
(arith_extended_reg32_i64 GPR32:$src2, arith_extend:$sh)), 4>;
31823188
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
31833189
XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
31843190
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
3185-
WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
3191+
WZR, GPR32:$src1,
3192+
(arith_shifted_reg32 GPR32:$src2, arith_shift32:$sh)), 4>;
31863193
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
3187-
XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
3194+
XZR, GPR64:$src1,
3195+
(arith_shifted_reg64 GPR64:$src2, arith_shift64:$sh)), 4>;
31883196

31893197
// Support negative immediates, e.g. cmp Rn, -imm -> cmn Rn, imm
31903198
def : InstSubst<cmpAlias#"\t$src, $imm", (!cast<Instruction>(NAME#"Wri")
@@ -3194,27 +3202,28 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
31943202

31953203
// Compare shorthands
31963204
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrs")
3197-
WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
3205+
WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)), 5>;
31983206
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrs")
3199-
XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
3207+
XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)), 5>;
32003208
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrx")
3201-
WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
3209+
WZR, GPR32sponly:$src1,
3210+
(arith_extended_reg32_i32 GPR32:$src2, 16)), 5>;
32023211
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
32033212
XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
32043213

32053214
// Register/register aliases with no shift when SP is not used.
32063215
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
3207-
GPR32, GPR32, GPR32, 0>;
3216+
GPR32, GPR32, (arith_shifted_reg32 GPR32:$src2, 0)>;
32083217
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
3209-
GPR64, GPR64, GPR64, 0>;
3218+
GPR64, GPR64, (arith_shifted_reg64 GPR64:$src2, 0)>;
32103219

32113220
// Register/register aliases with no shift when the first source register
32123221
// is SP.
32133222
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
3214-
GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
3215-
def : AddSubRegAlias<mnemonic,
3216-
!cast<Instruction>(NAME#"Xrx64"),
3217-
GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
3223+
GPR32, GPR32sponly,
3224+
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
3225+
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
3226+
GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
32183227
}
32193228

32203229
class AddSubG<bit isSub, string asm_inst, SDPatternOperator OpNode>
@@ -3399,9 +3408,10 @@ class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
33993408
}
34003409

34013410
// Aliases for register+register logical instructions.
3402-
class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
3411+
class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype,
3412+
dag op2>
34033413
: InstAlias<asm#"\t$dst, $src1, $src2",
3404-
(inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
3414+
(inst regtype:$dst, regtype:$src1, op2)>;
34053415

34063416
multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
34073417
string Alias> {
@@ -3473,10 +3483,10 @@ multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
34733483
let Inst{31} = 1;
34743484
}
34753485

3476-
def : LogicalRegAlias<mnemonic,
3477-
!cast<Instruction>(NAME#"Wrs"), GPR32>;
3478-
def : LogicalRegAlias<mnemonic,
3479-
!cast<Instruction>(NAME#"Xrs"), GPR64>;
3486+
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
3487+
GPR32, (logical_shifted_reg32 GPR32:$src2, 0)>;
3488+
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
3489+
GPR64, (logical_shifted_reg64 GPR64:$src2, 0)>;
34803490
}
34813491

34823492
// Split from LogicalReg to allow setting NZCV Defs
@@ -3496,10 +3506,10 @@ multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
34963506
}
34973507
} // Defs = [NZCV]
34983508

3499-
def : LogicalRegAlias<mnemonic,
3500-
!cast<Instruction>(NAME#"Wrs"), GPR32>;
3501-
def : LogicalRegAlias<mnemonic,
3502-
!cast<Instruction>(NAME#"Xrs"), GPR64>;
3509+
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
3510+
GPR32, (logical_shifted_reg32 GPR32:$src2, 0)>;
3511+
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
3512+
GPR64, (logical_shifted_reg64 GPR64:$src2, 0)>;
35033513
}
35043514

35053515
//---
@@ -3987,9 +3997,10 @@ class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
39873997
let Inst{4-0} = Rt;
39883998
}
39893999

3990-
class ROInstAlias<string asm, DAGOperand regtype, Instruction INST>
4000+
class ROInstAlias<string asm, DAGOperand regtype, Instruction INST,
4001+
ro_extend ext>
39914002
: InstAlias<asm # "\t$Rt, [$Rn, $Rm]",
3992-
(INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
4003+
(INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ext 0, 0))>;
39934004

39944005
multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
39954006
string asm, ValueType Ty, SDPatternOperator loadop> {
@@ -4015,7 +4026,7 @@ multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
40154026
let Inst{13} = 0b1;
40164027
}
40174028

4018-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4029+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend8>;
40194030
}
40204031

40214032
multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4040,7 +4051,7 @@ multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
40404051
let Inst{13} = 0b1;
40414052
}
40424053

4043-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4054+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend8>;
40444055
}
40454056

40464057
class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
@@ -4087,7 +4098,7 @@ multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
40874098
let Inst{13} = 0b1;
40884099
}
40894100

4090-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4101+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend16>;
40914102
}
40924103

40934104
multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4112,7 +4123,7 @@ multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
41124123
let Inst{13} = 0b1;
41134124
}
41144125

4115-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4126+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend16>;
41164127
}
41174128

41184129
class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
@@ -4159,7 +4170,7 @@ multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
41594170
let Inst{13} = 0b1;
41604171
}
41614172

4162-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4173+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend32>;
41634174
}
41644175

41654176
multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4184,7 +4195,7 @@ multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
41844195
let Inst{13} = 0b1;
41854196
}
41864197

4187-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4198+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend32>;
41884199
}
41894200

41904201
class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
@@ -4231,7 +4242,7 @@ multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
42314242
let Inst{13} = 0b1;
42324243
}
42334244

4234-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4245+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
42354246
}
42364247

42374248
multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4256,7 +4267,7 @@ multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
42564267
let Inst{13} = 0b1;
42574268
}
42584269

4259-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4270+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
42604271
}
42614272

42624273
class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
@@ -4303,7 +4314,7 @@ multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
43034314
let Inst{13} = 0b1;
43044315
}
43054316

4306-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4317+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend128>;
43074318
}
43084319

43094320
multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4324,7 +4335,7 @@ multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
43244335
let Inst{13} = 0b1;
43254336
}
43264337

4327-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4338+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend128>;
43284339
}
43294340

43304341
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
@@ -4373,9 +4384,7 @@ multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
43734384
let Inst{13} = 0b1;
43744385
}
43754386

4376-
def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
4377-
(!cast<Instruction>(NAME # "roX") prfop:$Rt,
4378-
GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
4387+
def : ROInstAlias<"prfm", prfop, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
43794388
}
43804389

43814390
//---

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 54 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -2416,13 +2416,17 @@ defm ADD : AddSub<0, "add", "sub", add>;
24162416
defm SUB : AddSub<1, "sub", "add">;
24172417

24182418
def : InstAlias<"mov $dst, $src",
2419-
(ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
2419+
(ADDWri GPR32sponly:$dst, GPR32sp:$src,
2420+
(addsub_shifted_imm32 0, 0))>;
24202421
def : InstAlias<"mov $dst, $src",
2421-
(ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
2422+
(ADDWri GPR32sp:$dst, GPR32sponly:$src,
2423+
(addsub_shifted_imm32 0, 0))>;
24222424
def : InstAlias<"mov $dst, $src",
2423-
(ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
2425+
(ADDXri GPR64sponly:$dst, GPR64sp:$src,
2426+
(addsub_shifted_imm64 0, 0))>;
24242427
def : InstAlias<"mov $dst, $src",
2425-
(ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
2428+
(ADDXri GPR64sp:$dst, GPR64sponly:$src,
2429+
(addsub_shifted_imm64 0, 0))>;
24262430

24272431
defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
24282432
defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
@@ -2482,19 +2486,31 @@ def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
24822486
(ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
24832487
}
24842488

2485-
def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
2486-
def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
2489+
def : InstAlias<"neg $dst, $src",
2490+
(SUBWrs GPR32:$dst, WZR,
2491+
(arith_shifted_reg32 GPR32:$src, 0)), 3>;
2492+
def : InstAlias<"neg $dst, $src",
2493+
(SUBXrs GPR64:$dst, XZR,
2494+
(arith_shifted_reg64 GPR64:$src, 0)), 3>;
24872495
def : InstAlias<"neg $dst, $src$shift",
2488-
(SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
2496+
(SUBWrs GPR32:$dst, WZR,
2497+
(arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)), 2>;
24892498
def : InstAlias<"neg $dst, $src$shift",
2490-
(SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
2491-
2492-
def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
2493-
def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
2499+
(SUBXrs GPR64:$dst, XZR,
2500+
(arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)), 2>;
2501+
2502+
def : InstAlias<"negs $dst, $src",
2503+
(SUBSWrs GPR32:$dst, WZR,
2504+
(arith_shifted_reg32 GPR32:$src, 0)), 3>;
2505+
def : InstAlias<"negs $dst, $src",
2506+
(SUBSXrs GPR64:$dst, XZR,
2507+
(arith_shifted_reg64 GPR64:$src, 0)), 3>;
24942508
def : InstAlias<"negs $dst, $src$shift",
2495-
(SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
2509+
(SUBSWrs GPR32:$dst, WZR,
2510+
(arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)), 2>;
24962511
def : InstAlias<"negs $dst, $src$shift",
2497-
(SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
2512+
(SUBSXrs GPR64:$dst, XZR,
2513+
(arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)), 2>;
24982514

24992515

25002516
// Unsigned/Signed divide
@@ -2921,31 +2937,45 @@ defm ORN : LogicalReg<0b01, 1, "orn",
29212937
BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
29222938
defm ORR : LogicalReg<0b01, 0, "orr", or>;
29232939

2924-
def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
2925-
def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
2926-
2927-
def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
2928-
def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
2940+
def : InstAlias<"mov $dst, $src",
2941+
(ORRWrs GPR32:$dst, WZR,
2942+
(logical_shifted_reg32 GPR32:$src, 0)), 2>;
2943+
def : InstAlias<"mov $dst, $src",
2944+
(ORRXrs GPR64:$dst, XZR,
2945+
(logical_shifted_reg64 GPR64:$src, 0)), 2>;
2946+
2947+
def : InstAlias<"mvn $Wd, $Wm",
2948+
(ORNWrs GPR32:$Wd, WZR,
2949+
(logical_shifted_reg32 GPR32:$Wm, 0)), 3>;
2950+
def : InstAlias<"mvn $Xd, $Xm",
2951+
(ORNXrs GPR64:$Xd, XZR,
2952+
(logical_shifted_reg64 GPR64:$Xm, 0)), 3>;
29292953

29302954
def : InstAlias<"mvn $Wd, $Wm$sh",
2931-
(ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
2955+
(ORNWrs GPR32:$Wd, WZR,
2956+
(logical_shifted_reg32 GPR32:$Wm, logical_shift32:$sh)), 2>;
29322957
def : InstAlias<"mvn $Xd, $Xm$sh",
2933-
(ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
2958+
(ORNXrs GPR64:$Xd, XZR,
2959+
(logical_shifted_reg64 GPR64:$Xm, logical_shift64:$sh)), 2>;
29342960

29352961
def : InstAlias<"tst $src1, $src2",
29362962
(ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
29372963
def : InstAlias<"tst $src1, $src2",
29382964
(ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
29392965

29402966
def : InstAlias<"tst $src1, $src2",
2941-
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
2967+
(ANDSWrs WZR, GPR32:$src1,
2968+
(logical_shifted_reg32 GPR32:$src2, 0)), 3>;
29422969
def : InstAlias<"tst $src1, $src2",
2943-
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
2970+
(ANDSXrs XZR, GPR64:$src1,
2971+
(logical_shifted_reg64 GPR64:$src2, 0)), 3>;
29442972

29452973
def : InstAlias<"tst $src1, $src2$sh",
2946-
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
2974+
(ANDSWrs WZR, GPR32:$src1,
2975+
(logical_shifted_reg32 GPR32:$src2, logical_shift32:$sh)), 2>;
29472976
def : InstAlias<"tst $src1, $src2$sh",
2948-
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
2977+
(ANDSXrs XZR, GPR64:$src1,
2978+
(logical_shifted_reg64 GPR64:$src2, logical_shift64:$sh)), 2>;
29492979

29502980

29512981
def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;

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