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‎llvm/test/Transforms/InstCombine/ceil-shift.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i1 @ceil_shift4(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift4(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP6]], [[TMP4]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = lshr i32 %arg0, 4
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%2 = and i32 %arg0, 15
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%3 = icmp ne i32 %2, 0
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%4 = zext i1 %3 to i32
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%5 = add i32 %1, %4
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%6 = icmp eq i32 %5, 0
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ret i1 %6
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}
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define i1 @ceil_shift6(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift6(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[ARG0]], 6
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 63
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP6]], [[TMP4]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = lshr i32 %arg0, 6
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%2 = and i32 %arg0, 63
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%3 = icmp ne i32 %2, 0
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%4 = zext i1 %3 to i32
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%5 = add i32 %1, %4
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%6 = icmp eq i32 %5, 0
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ret i1 %6
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}
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define i1 @ceil_shift11(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift11(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[ARG0]], 11
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 2047
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP6]], [[TMP4]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = lshr i32 %arg0, 11
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%2 = and i32 %arg0, 2047
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%3 = icmp ne i32 %2, 0
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%4 = zext i1 %3 to i32
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%5 = add i32 %1, %4
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%6 = icmp eq i32 %5, 0
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ret i1 %6
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}
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define i1 @ceil_shift0(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift0(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[ARG0]], 0
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; CHECK-NEXT: ret i1 [[TMP1]]
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;
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%1 = lshr i32 %arg0, 0
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%2 = and i32 %arg0, 0
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%3 = icmp ne i32 %2, 0
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%4 = zext i1 %3 to i32
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%5 = add i32 %1, %4
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%6 = icmp eq i32 %5, 0
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ret i1 %6
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}
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declare void @use(i32)
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define i1 @ceil_shift4_used_1(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift4_used_1(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: call void @use(i32 [[TMP1]])
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP1]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%1 = lshr i32 %arg0, 4
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call void @use(i32 %1)
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%2 = and i32 %arg0, 15
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%3 = icmp ne i32 %2, 0
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%4 = zext i1 %3 to i32
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%5 = add i32 %1, %4
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%6 = icmp eq i32 %5, 0
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ret i1 %6
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}
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define i1 @ceil_shift4_used_5(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift4_used_5(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw i32 [[TMP1]], [[TMP4]]
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; CHECK-NEXT: call void @use(i32 [[TMP5]])
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%1 = lshr i32 %arg0, 4
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%2 = and i32 %arg0, 15
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%3 = icmp ne i32 %2, 0
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%4 = zext i1 %3 to i32
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%5 = add i32 %1, %4
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call void @use(i32 %5)
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%6 = icmp eq i32 %5, 0
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ret i1 %6
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}
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define <4 x i1> @ceil_shift4_v4i32(<4 x i32> %arg0) {
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; CHECK-LABEL: define <4 x i1> @ceil_shift4_v4i32(
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; CHECK-SAME: <4 x i32> [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP6:%.*]] = lshr <4 x i32> [[ARG0]], splat (i32 16)
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; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[ARG0]], splat (i32 65535)
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i1> [[TMP3]] to <4 x i32>
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; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> [[TMP6]], [[TMP4]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[TMP5]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[TMP1]]
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;
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%1 = lshr <4 x i32> %arg0, splat (i32 16)
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%2 = and <4 x i32> %arg0, splat (i32 65535)
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%3 = icmp ne <4 x i32> %2, zeroinitializer
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%4 = zext <4 x i1> %3 to <4 x i32>
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%5 = add <4 x i32> %1, %4
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%6 = icmp eq <4 x i32> %5, zeroinitializer
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ret <4 x i1> %6
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}
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define <8 x i1> @ceil_shift4_v8i16(<8 x i16> %arg0) {
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; CHECK-LABEL: define <8 x i1> @ceil_shift4_v8i16(
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; CHECK-SAME: <8 x i16> [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP6:%.*]] = lshr <8 x i16> [[ARG0]], splat (i16 4)
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; CHECK-NEXT: [[TMP2:%.*]] = and <8 x i16> [[ARG0]], splat (i16 15)
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i1> [[TMP3]] to <8 x i16>
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; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i16> [[TMP6]], [[TMP4]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <8 x i16> [[TMP5]], zeroinitializer
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; CHECK-NEXT: ret <8 x i1> [[TMP1]]
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;
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%1 = lshr <8 x i16> %arg0, splat (i16 4)
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%2 = and <8 x i16> %arg0, splat (i16 15)
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%3 = icmp ne <8 x i16> %2, zeroinitializer
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%4 = zext <8 x i1> %3 to <8 x i16>
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%5 = add <8 x i16> %1, %4
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%6 = icmp eq <8 x i16> %5, zeroinitializer
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ret <8 x i1> %6
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}
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; negative tests
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define i1 @ceil_shift_not_mask_1(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift_not_mask_1(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 31
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP1]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%1 = lshr i32 %arg0, 4
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%2 = and i32 %arg0, 31
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%3 = icmp ne i32 %2, 0
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%4 = zext i1 %3 to i32
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%5 = add i32 %1, %4
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%6 = icmp eq i32 %5, 0
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ret i1 %6
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}
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define i1 @ceil_shift_not_mask_2(i32 %arg0) {
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; CHECK-LABEL: define i1 @ceil_shift_not_mask_2(
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; CHECK-SAME: i32 [[ARG0:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[ARG0]], 5
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARG0]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP1]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
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; CHECK-NEXT: ret i1 [[TMP6]]
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;
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%1 = lshr i32 %arg0, 5
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%2 = and i32 %arg0, 15
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%3 = icmp ne i32 %2, 0
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%4 = zext i1 %3 to i32
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%5 = add i32 %1, %4
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%6 = icmp eq i32 %5, 0
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ret i1 %6
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}

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