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1 parent ff4132e commit 8d8ce6eCopy full SHA for 8d8ce6e
llvm/test/CodeGen/RISCV/pr135206.ll
@@ -44,7 +44,7 @@ define i1 @foo() nounwind "probe-stack"="inline-asm" "target-features"="+v" {
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addiw a0, a0, 32
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; CHECK-NEXT: add a0, sp, a0
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-; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
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; CHECK-NEXT: addiw a0, a1, 1622
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; CHECK-NEXT: vse8.v v8, (s0)
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; CHECK-NEXT: vse8.v v8, (s1)
@@ -56,7 +56,7 @@ define i1 @foo() nounwind "probe-stack"="inline-asm" "target-features"="+v" {
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-; CHECK-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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