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Aditi-Medhane
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[PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction Support
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7 files changed

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‎clang/include/clang/Basic/BuiltinsPPC.def‎

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Original file line numberDiff line numberDiff line change
@@ -515,6 +515,10 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector")
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TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
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TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
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//P9 BCD builtins
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TARGET_BUILTIN(__builtin_ppc_bcdcopysign, "V16UcV16UcV16Uc", "", "power9-vector")
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TARGET_BUILTIN(__builtin_ppc_bcdsetsign, "V16UcV16UcUc", "t", "power9-vector")
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// P7 BCD builtins.
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TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions")
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TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions")

‎clang/lib/Basic/Targets/PPC.cpp‎

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@@ -88,6 +88,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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}
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static void defineXLCompatMacros(MacroBuilder &Builder) {
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Builder.defineMacro("__builtin_bcdcopysign", "__builtin_ppc_bcdcopysign");
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Builder.defineMacro("__builtin_bcdsetsign", "__builtin_ppc_bcdsetsign");
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Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd");
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Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd");
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Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s");

‎clang/lib/Sema/SemaPPC.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -106,6 +106,8 @@ bool SemaPPC::CheckPPCBuiltinFunctionCall(const TargetInfo &TI,
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switch (BuiltinID) {
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default:
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return false;
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case PPC::BI__builtin_ppc_bcdsetsign:
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return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1);
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case PPC::BI__builtin_altivec_crypto_vshasigmaw:
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case PPC::BI__builtin_altivec_crypto_vshasigmad:
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return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1) ||

‎clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c‎

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@@ -0,0 +1,29 @@
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// NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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// REQUIRES: powerpc-registered-target
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// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -O2 -target-cpu pwr9 \
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// RUN: -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -O2 -target-cpu pwr9 \
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// RUN: -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc-unknown-unknown -O2 -target-cpu pwr9 \
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// RUN: -emit-llvm %s -o - | FileCheck %s
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// CHECK-LABEL: test_bcdcopysign
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// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8> %a, <16 x i8> %b)
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// CHECK-NEXT: ret <16 x i8> [[TMP0]]
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vector unsigned char test_bcdcopysign(vector unsigned char a, vector unsigned char b) {
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return __builtin_ppc_bcdcopysign(a, b);
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}
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// CHECK-LABEL: test_bcdsetsign_imm0
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// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 0)
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// CHECK-NEXT: ret <16 x i8> [[TMP0]]
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vector unsigned char test_bcdsetsign_imm0(vector unsigned char a) {
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return __builtin_ppc_bcdsetsign(a, '\0');
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}
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// CHECK-LABEL: test_bcdsetsign_imm1
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// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 1)
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// CHECK-NEXT: ret <16 x i8> [[TMP0]]
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vector unsigned char test_bcdsetsign_imm1(vector unsigned char a) {
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return __builtin_ppc_bcdsetsign(a, '\1');
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}

‎llvm/include/llvm/IR/IntrinsicsPowerPC.td‎

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Original file line numberDiff line numberDiff line change
@@ -668,6 +668,14 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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def int_ppc_addg6s: ClangBuiltin<"__builtin_addg6s">,
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DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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// BCD Format conversion intrinsics
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def int_ppc_bcdcopysign : ClangBuiltin<"__builtin_ppc_bcdcopysign">,
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DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
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def int_ppc_bcdsetsign : ClangBuiltin<"__builtin_ppc_bcdsetsign">,
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DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<1>>]>;
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def int_ppc_bcdadd : ClangBuiltin<"__builtin_ppc_bcdadd">,
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DefaultAttrsIntrinsic<
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[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],

‎llvm/lib/Target/PowerPC/PPCInstrAltivec.td‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1626,9 +1626,11 @@ def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>;
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// Decimal Copy-Sign/Set-Sign
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let Defs = [CR6] in
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def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
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def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.",
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[(set v16i8:$VD, (int_ppc_bcdcopysign v16i8:$VA, v16i8:$VB))]>;
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1631-
def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
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def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.",
1633+
[(set v16i8:$VD, (int_ppc_bcdsetsign v16i8:$VB, i32:$PS))]>;
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// Decimal Shift/Unsigned-Shift/Shift-and-Round
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def BCDS_rec : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;

‎llvm/test/CodeGen/PowerPC/builtins-bcd-helpers.ll‎

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@@ -0,0 +1,40 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 \
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; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr9 \
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; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
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define dso_local <16 x i8> @test_bcdcopysign(<16 x i8> noundef %a, <16 x i8> noundef %b) {
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; CHECK-LABEL: test_bcdcopysign:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bcdcpsgn. v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %0
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}
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define dso_local <16 x i8> @test_bcdsetsign_imm0(<16 x i8> noundef %a) {
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; CHECK-LABEL: test_bcdsetsign_imm0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bcdsetsgn. v2, v2, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 0)
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ret <16 x i8> %0
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}
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define dso_local <16 x i8> @test_bcdsetsign_imm1(<16 x i8> noundef %a) {
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; CHECK-LABEL: test_bcdsetsign_imm1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bcdsetsgn. v2, v2, 1
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 1)
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ret <16 x i8> %0
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}
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declare <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8>, i32)

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