Skip to content

Commit 8e53a88

Browse files
SavchenkoValeriySavchenkoValeriy
authored
[DAGCombiner] Handle type-promoted constants in SDIV lowering (#169924)
Builds up on the solution proposed for #169491 and applies it for SDIV as well.
1 parent dd6e87b commit 8e53a88

File tree

4 files changed

+103
-77
lines changed

4 files changed

+103
-77
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5186,7 +5186,8 @@ static bool isDivisorPowerOfTwo(SDValue Divisor) {
51865186
return false;
51875187
};
51885188

5189-
return ISD::matchUnaryPredicate(Divisor, IsPowerOfTwo);
5189+
return ISD::matchUnaryPredicate(Divisor, IsPowerOfTwo, /*AllowUndefs=*/false,
5190+
/*AllowTruncation=*/true);
51905191
}
51915192

51925193
SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
@@ -5250,7 +5251,8 @@ SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
52505251
// alternate sequence. Targets may check function attributes for size/speed
52515252
// trade-offs.
52525253
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
5253-
if (isConstantOrConstantVector(N1) &&
5254+
if (isConstantOrConstantVector(N1, /*NoOpaques=*/false,
5255+
/*AllowTruncation=*/true) &&
52545256
!TLI.isIntDivCheap(N->getValueType(0), Attr))
52555257
if (SDValue Op = BuildSDIV(N))
52565258
return Op;

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6564,8 +6564,9 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
65646564
auto BuildSDIVPattern = [&](ConstantSDNode *C) {
65656565
if (C->isZero())
65666566
return false;
6567-
6568-
const APInt &Divisor = C->getAPIntValue();
6567+
// Truncate the divisor to the target scalar type in case it was promoted
6568+
// during type legalization.
6569+
APInt Divisor = C->getAPIntValue().trunc(EltBits);
65696570
SignedDivisionByConstantInfo magics = SignedDivisionByConstantInfo::get(Divisor);
65706571
int NumeratorFactor = 0;
65716572
int ShiftMask = -1;
@@ -6595,7 +6596,8 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
65956596
SDValue N1 = N->getOperand(1);
65966597

65976598
// Collect the shifts / magic values from each element.
6598-
if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern))
6599+
if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern, /*AllowUndefs=*/false,
6600+
/*AllowTruncation=*/true))
65996601
return SDValue();
66006602

66016603
SDValue MagicFactor, Factor, Shift, ShiftMask;

‎llvm/test/CodeGen/AArch64/rem-by-const.ll‎

Lines changed: 17 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -893,46 +893,15 @@ define <4 x i8> @sv4i8_7(<4 x i8> %d, <4 x i8> %e) {
893893
; CHECK-SD-LABEL: sv4i8_7:
894894
; CHECK-SD: // %bb.0: // %entry
895895
; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
896-
; CHECK-SD-NEXT: mov x8, #-56173 // =0xffffffffffff2493
897-
; CHECK-SD-NEXT: movk x8, #37449, lsl #16
896+
; CHECK-SD-NEXT: mov w8, #18725 // =0x4925
897+
; CHECK-SD-NEXT: movi v2.4h, #7
898+
; CHECK-SD-NEXT: dup v1.4h, w8
898899
; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8
899-
; CHECK-SD-NEXT: smov x10, v0.h[0]
900-
; CHECK-SD-NEXT: smov x9, v0.h[1]
901-
; CHECK-SD-NEXT: smov w12, v0.h[0]
902-
; CHECK-SD-NEXT: smov w11, v0.h[1]
903-
; CHECK-SD-NEXT: smov x13, v0.h[2]
904-
; CHECK-SD-NEXT: smov w14, v0.h[2]
905-
; CHECK-SD-NEXT: smov x17, v0.h[3]
906-
; CHECK-SD-NEXT: smull x10, w10, w8
907-
; CHECK-SD-NEXT: smull x9, w9, w8
908-
; CHECK-SD-NEXT: smull x13, w13, w8
909-
; CHECK-SD-NEXT: add x10, x12, x10, lsr #32
910-
; CHECK-SD-NEXT: smull x8, w17, w8
911-
; CHECK-SD-NEXT: add x9, x11, x9, lsr #32
912-
; CHECK-SD-NEXT: asr w16, w10, #2
913-
; CHECK-SD-NEXT: add x13, x14, x13, lsr #32
914-
; CHECK-SD-NEXT: asr w15, w9, #2
915-
; CHECK-SD-NEXT: add w10, w16, w10, lsr #31
916-
; CHECK-SD-NEXT: asr w16, w13, #2
917-
; CHECK-SD-NEXT: add w9, w15, w9, lsr #31
918-
; CHECK-SD-NEXT: smov w15, v0.h[3]
919-
; CHECK-SD-NEXT: sub w10, w10, w10, lsl #3
920-
; CHECK-SD-NEXT: sub w9, w9, w9, lsl #3
921-
; CHECK-SD-NEXT: add w10, w12, w10
922-
; CHECK-SD-NEXT: fmov s0, w10
923-
; CHECK-SD-NEXT: add w9, w11, w9
924-
; CHECK-SD-NEXT: add w10, w16, w13, lsr #31
925-
; CHECK-SD-NEXT: add x8, x15, x8, lsr #32
926-
; CHECK-SD-NEXT: mov v0.h[1], w9
927-
; CHECK-SD-NEXT: sub w9, w10, w10, lsl #3
928-
; CHECK-SD-NEXT: asr w10, w8, #2
929-
; CHECK-SD-NEXT: add w9, w14, w9
930-
; CHECK-SD-NEXT: add w8, w10, w8, lsr #31
931-
; CHECK-SD-NEXT: mov v0.h[2], w9
932-
; CHECK-SD-NEXT: sub w8, w8, w8, lsl #3
933-
; CHECK-SD-NEXT: add w8, w15, w8
934-
; CHECK-SD-NEXT: mov v0.h[3], w8
935-
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
900+
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
901+
; CHECK-SD-NEXT: sshr v1.4s, v1.4s, #17
902+
; CHECK-SD-NEXT: xtn v1.4h, v1.4s
903+
; CHECK-SD-NEXT: usra v1.4h, v1.4h, #15
904+
; CHECK-SD-NEXT: mls v0.4h, v1.4h, v2.4h
936905
; CHECK-SD-NEXT: ret
937906
;
938907
; CHECK-GI-LABEL: sv4i8_7:
@@ -978,39 +947,15 @@ define <4 x i8> @sv4i8_100(<4 x i8> %d, <4 x i8> %e) {
978947
; CHECK-SD-LABEL: sv4i8_100:
979948
; CHECK-SD: // %bb.0: // %entry
980949
; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
981-
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
982-
; CHECK-SD-NEXT: mov w14, #100 // =0x64
983-
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
984-
; CHECK-SD-NEXT: sshr v1.4h, v0.4h, #8
985-
; CHECK-SD-NEXT: smov x9, v1.h[0]
986-
; CHECK-SD-NEXT: smov x10, v1.h[1]
987-
; CHECK-SD-NEXT: smov x11, v1.h[2]
988-
; CHECK-SD-NEXT: smov w12, v1.h[0]
989-
; CHECK-SD-NEXT: smov x13, v1.h[3]
990-
; CHECK-SD-NEXT: smov w15, v1.h[1]
991-
; CHECK-SD-NEXT: smull x9, w9, w8
992-
; CHECK-SD-NEXT: smull x10, w10, w8
993-
; CHECK-SD-NEXT: smull x11, w11, w8
994-
; CHECK-SD-NEXT: asr x9, x9, #37
995-
; CHECK-SD-NEXT: smull x8, w13, w8
996-
; CHECK-SD-NEXT: asr x10, x10, #37
997-
; CHECK-SD-NEXT: add w9, w9, w9, lsr #31
998-
; CHECK-SD-NEXT: asr x11, x11, #37
999-
; CHECK-SD-NEXT: add w10, w10, w10, lsr #31
1000-
; CHECK-SD-NEXT: asr x8, x8, #37
1001-
; CHECK-SD-NEXT: msub w9, w9, w14, w12
1002-
; CHECK-SD-NEXT: msub w10, w10, w14, w15
1003-
; CHECK-SD-NEXT: add w8, w8, w8, lsr #31
1004-
; CHECK-SD-NEXT: fmov s0, w9
1005-
; CHECK-SD-NEXT: add w9, w11, w11, lsr #31
1006-
; CHECK-SD-NEXT: smov w11, v1.h[2]
1007-
; CHECK-SD-NEXT: msub w9, w9, w14, w11
1008-
; CHECK-SD-NEXT: mov v0.h[1], w10
1009-
; CHECK-SD-NEXT: smov w10, v1.h[3]
1010-
; CHECK-SD-NEXT: msub w8, w8, w14, w10
1011-
; CHECK-SD-NEXT: mov v0.h[2], w9
1012-
; CHECK-SD-NEXT: mov v0.h[3], w8
1013-
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
950+
; CHECK-SD-NEXT: mov w8, #5243 // =0x147b
951+
; CHECK-SD-NEXT: movi v2.4h, #100
952+
; CHECK-SD-NEXT: dup v1.4h, w8
953+
; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8
954+
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
955+
; CHECK-SD-NEXT: sshr v1.4s, v1.4s, #19
956+
; CHECK-SD-NEXT: xtn v1.4h, v1.4s
957+
; CHECK-SD-NEXT: usra v1.4h, v1.4h, #15
958+
; CHECK-SD-NEXT: mls v0.4h, v1.4h, v2.4h
1014959
; CHECK-SD-NEXT: ret
1015960
;
1016961
; CHECK-GI-LABEL: sv4i8_100:

‎llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
3+
4+
define <8 x i16> @sdiv_v8i16_by_7(<8 x i16> %x) {
5+
; CHECK-LABEL: sdiv_v8i16_by_7:
6+
; CHECK: // %bb.0:
7+
; CHECK-NEXT: mov w8, #18725 // =0x4925
8+
; CHECK-NEXT: dup v1.8h, w8
9+
; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
10+
; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
11+
; CHECK-NEXT: uzp2 v0.8h, v0.8h, v2.8h
12+
; CHECK-NEXT: sshr v0.8h, v0.8h, #1
13+
; CHECK-NEXT: usra v0.8h, v0.8h, #15
14+
; CHECK-NEXT: ret
15+
%div = sdiv <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
16+
ret <8 x i16> %div
17+
}
18+
19+
define <16 x i16> @sdiv_v16i16_by_7(<16 x i16> %x) {
20+
; CHECK-LABEL: sdiv_v16i16_by_7:
21+
; CHECK: // %bb.0:
22+
; CHECK-NEXT: mov w8, #18725 // =0x4925
23+
; CHECK-NEXT: dup v2.8h, w8
24+
; CHECK-NEXT: smull2 v3.4s, v0.8h, v2.8h
25+
; CHECK-NEXT: smull v0.4s, v0.4h, v2.4h
26+
; CHECK-NEXT: smull2 v4.4s, v1.8h, v2.8h
27+
; CHECK-NEXT: smull v1.4s, v1.4h, v2.4h
28+
; CHECK-NEXT: uzp2 v0.8h, v0.8h, v3.8h
29+
; CHECK-NEXT: uzp2 v1.8h, v1.8h, v4.8h
30+
; CHECK-NEXT: sshr v0.8h, v0.8h, #1
31+
; CHECK-NEXT: sshr v1.8h, v1.8h, #1
32+
; CHECK-NEXT: usra v0.8h, v0.8h, #15
33+
; CHECK-NEXT: usra v1.8h, v1.8h, #15
34+
; CHECK-NEXT: ret
35+
%div = sdiv <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
36+
ret <16 x i16> %div
37+
}
38+
39+
define <8 x i16> @srem_v8i16_by_7(<8 x i16> %x) {
40+
; CHECK-LABEL: srem_v8i16_by_7:
41+
; CHECK: // %bb.0:
42+
; CHECK-NEXT: mov w8, #18725 // =0x4925
43+
; CHECK-NEXT: dup v1.8h, w8
44+
; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
45+
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
46+
; CHECK-NEXT: uzp2 v1.8h, v1.8h, v2.8h
47+
; CHECK-NEXT: movi v2.8h, #7
48+
; CHECK-NEXT: sshr v1.8h, v1.8h, #1
49+
; CHECK-NEXT: usra v1.8h, v1.8h, #15
50+
; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h
51+
; CHECK-NEXT: ret
52+
%rem = srem <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
53+
ret <8 x i16> %rem
54+
}
55+
56+
define <16 x i16> @srem_v16i16_by_7(<16 x i16> %x) {
57+
; CHECK-LABEL: srem_v16i16_by_7:
58+
; CHECK: // %bb.0:
59+
; CHECK-NEXT: mov w8, #18725 // =0x4925
60+
; CHECK-NEXT: dup v2.8h, w8
61+
; CHECK-NEXT: smull2 v3.4s, v0.8h, v2.8h
62+
; CHECK-NEXT: smull v4.4s, v0.4h, v2.4h
63+
; CHECK-NEXT: smull2 v5.4s, v1.8h, v2.8h
64+
; CHECK-NEXT: smull v2.4s, v1.4h, v2.4h
65+
; CHECK-NEXT: uzp2 v3.8h, v4.8h, v3.8h
66+
; CHECK-NEXT: movi v4.8h, #7
67+
; CHECK-NEXT: uzp2 v2.8h, v2.8h, v5.8h
68+
; CHECK-NEXT: sshr v3.8h, v3.8h, #1
69+
; CHECK-NEXT: sshr v2.8h, v2.8h, #1
70+
; CHECK-NEXT: usra v3.8h, v3.8h, #15
71+
; CHECK-NEXT: usra v2.8h, v2.8h, #15
72+
; CHECK-NEXT: mls v0.8h, v3.8h, v4.8h
73+
; CHECK-NEXT: mls v1.8h, v2.8h, v4.8h
74+
; CHECK-NEXT: ret
75+
%rem = srem <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
76+
ret <16 x i16> %rem
77+
}

0 commit comments

Comments
 (0)