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WIP attempt to avoid MCRegAliasIterator
1 parent 9624e4d commit 8e9bc38

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4 files changed

+91
-78
lines changed

4 files changed

+91
-78
lines changed

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 30 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2234,25 +2234,43 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
22342234
return true;
22352235
}
22362236

2237-
static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
2238-
const TargetRegisterInfo *TRI) {
2239-
for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
2240-
if (MBB.isLiveIn(*R)) {
2241-
return true;
2242-
}
2243-
}
2244-
return false;
2245-
}
2246-
22472237
bool SIFrameLowering::spillCalleeSavedRegisters(
22482238
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
22492239
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
22502240
MachineFunction *MF = MBB.getParent();
22512241
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
22522242
const SIInstrInfo *TII = ST.getInstrInfo();
22532243
const SIRegisterInfo *SITRI = static_cast<const SIRegisterInfo *>(TRI);
2244+
const MachineRegisterInfo &MRI = MF->getRegInfo();
22542245

22552246
if (!ST.useVGPRBlockOpsForCSR()) {
2247+
SparseBitVector<> LiveInRoots;
2248+
if (MRI.tracksLiveness()) {
2249+
for (const auto &LI : MBB.liveins()) {
2250+
for (MCRegUnitMaskIterator MI(LI.PhysReg, TRI); MI.isValid(); ++MI) {
2251+
auto [Unit, UnitLaneMask] = *MI;
2252+
if ((LI.LaneMask & UnitLaneMask).none())
2253+
continue;
2254+
for (MCRegUnitRootIterator RI(Unit, TRI); RI.isValid(); ++RI)
2255+
LiveInRoots.set(*RI);
2256+
}
2257+
}
2258+
}
2259+
2260+
auto UpdateLiveInCheckCanKill = [&](MCRegister Reg) {
2261+
if (!MRI.tracksLiveness())
2262+
return false;
2263+
for (MCRegUnitIterator UI(Reg, TRI); UI.isValid(); ++UI) {
2264+
for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
2265+
if (LiveInRoots.test(*RI))
2266+
return false;
2267+
}
2268+
}
2269+
// Reg is live in to the spill
2270+
MBB.addLiveIn(Reg);
2271+
return true;
2272+
};
2273+
22562274
for (const CalleeSavedInfo &CS : CSI) {
22572275
// Insert the spill to the stack frame.
22582276
unsigned Reg = CS.getReg();
@@ -2268,9 +2286,8 @@ bool SIFrameLowering::spillCalleeSavedRegisters(
22682286
// the incoming register value, so don't kill at the spill point. This
22692287
// happens since we pass some special inputs (workgroup IDs) in the
22702288
// callee saved range.
2271-
const bool IsLiveIn = isLiveIntoMBB(Reg, MBB, TRI);
2272-
TII->storeRegToStackSlotCFI(MBB, MI, Reg, !IsLiveIn, CS.getFrameIdx(),
2273-
RC, TRI);
2289+
TII->storeRegToStackSlotCFI(MBB, MI, Reg, UpdateLiveInCheckCanKill(Reg),
2290+
CS.getFrameIdx(), RC, TRI);
22742291
}
22752292
}
22762293
return true;

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