[AMDGPU] Support s_endpgm_ordered_ps_done on GFX11 (#119230)

Support assembly/disassembly of this instruction for compatibility with
SP3, even though it has no use in GFX11. It is fully removed in GFX12.

Author: jayfoad

llvm/lib/Target/AMDGPU/AMDGPU.td

@@ -2136,6 +2136,11 @@ def isGFX9GFX10 :
             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
   AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX11Insts))>;
 
+def isGFX9GFX10GFX11 :
+  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9 &&"
+            "Subtarget->getGeneration() < AMDGPUSubtarget::GFX12">,
+  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX12Insts))>;
+
 def isGFX8GFX9GFX10 :
   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"

llvm/lib/Target/AMDGPU/SOPInstructions.td

@@ -1512,12 +1512,12 @@ def S_ENDPGM_SAVED : SOPP_Pseudo<"s_endpgm_saved", (ins)> {
   let isReturn = 1;
 }
 
-let SubtargetPredicate = isGFX9GFX10 in {
+let SubtargetPredicate = isGFX9GFX10GFX11 in {
   let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
     def S_ENDPGM_ORDERED_PS_DONE :
       SOPP_Pseudo<"s_endpgm_ordered_ps_done", (ins)>;
   } // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1
-} // End SubtargetPredicate = isGFX9GFX10
+} // End SubtargetPredicate = isGFX9GFX10GFX11
 
 let SubtargetPredicate = isGFX10Plus in {
   let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
@@ -2661,6 +2661,7 @@ defm S_CBRANCH_CDBGSYS_OR_USER    : SOPP_Real_With_Relaxation_gfx11<0x029>;
 defm S_CBRANCH_CDBGSYS_AND_USER   : SOPP_Real_With_Relaxation_gfx11<0x02a>;
 defm S_ENDPGM                     : SOPP_Real_32_gfx11_gfx12<0x030>;
 defm S_ENDPGM_SAVED               : SOPP_Real_32_gfx11_gfx12<0x031>;
+defm S_ENDPGM_ORDERED_PS_DONE     : SOPP_Real_32_gfx11<0x032>;
 defm S_WAKEUP                     : SOPP_Real_32_gfx11_gfx12<0x034>;
 defm S_SETPRIO                    : SOPP_Real_32_gfx11_gfx12<0x035>;
 defm S_SENDMSG                    : SOPP_Real_32_gfx11_gfx12<0x036>;

llvm/test/MC/AMDGPU/gfx11_asm_sopp.s

@@ -430,3 +430,6 @@ s_wait_event 0x3141
 
 s_wait_event 0xc1d1
 // GFX11: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf]
+
+s_endpgm_ordered_ps_done
+// GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]

llvm/test/MC/AMDGPU/gfx12_err.s

@@ -113,3 +113,6 @@ s_prefetch_inst s[14:15], 0xffffff, m0, 7
 // GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 24-bit signed offset
 // GFX12-ERR: s_prefetch_inst s[14:15], 0xffffff, m0, 7
 // GFX12-ERR:                           ^
+
+s_endpgm_ordered_ps_done
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU

llvm/test/MC/AMDGPU/sopk.s

@@ -478,7 +478,7 @@ s_endpgm_ordered_ps_done
 // GFX9:     s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
 // NOSICIVI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
 // GFX10: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
-// NOGFX11: :[[@LINE-4]]:{{[0-9]+}}: error: instruction not supported on this GPU
+// GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf]
 
 s_call_b64 null, 12609
 // GFX10: s_call_b64 null, 12609 ; encoding: [0x41,0x31,0x7d,0xbb]

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt

@@ -294,3 +294,6 @@
 
 # GFX11: s_wait_event 0xc1d1                     ; encoding: [0xd1,0xc1,0x8b,0xbf]
 0xd1,0xc1,0x8b,0xbf
+
+# GFX11: s_endpgm_ordered_ps_done                ; encoding: [0x00,0x00,0xb2,0xbf]
+0x00,0x00,0xb2,0xbf