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mikhailramalhomikhailramalho
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Readded test
Signed-off-by: Mikhail R. Gadelha <[email protected]>
1 parent 1cfa8b4 commit 8eb53a9

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‎llvm/test/CodeGen/RISCV/rvv/intrinsic-vector-match.ll‎

Lines changed: 384 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -842,6 +842,390 @@ define <vscale x 16 x i1> @match_nxv16i8_v32i8(<vscale x 16 x i8> %op1, <32 x i8
842842
ret <vscale x 16 x i1> %r
843843
}
844844

845+
define <16 x i1> @match_v16i8_v32i8(<16 x i8> %op1, <32 x i8> %op2, <16 x i1> %mask) {
846+
; RV32-LABEL: match_v16i8_v32i8:
847+
; RV32: # %bb.0:
848+
; RV32-NEXT: addi sp, sp, -64
849+
; RV32-NEXT: .cfi_def_cfa_offset 64
850+
; RV32-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
851+
; RV32-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
852+
; RV32-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
853+
; RV32-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
854+
; RV32-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
855+
; RV32-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
856+
; RV32-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
857+
; RV32-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
858+
; RV32-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
859+
; RV32-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
860+
; RV32-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
861+
; RV32-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
862+
; RV32-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
863+
; RV32-NEXT: .cfi_offset ra, -4
864+
; RV32-NEXT: .cfi_offset s0, -8
865+
; RV32-NEXT: .cfi_offset s1, -12
866+
; RV32-NEXT: .cfi_offset s2, -16
867+
; RV32-NEXT: .cfi_offset s3, -20
868+
; RV32-NEXT: .cfi_offset s4, -24
869+
; RV32-NEXT: .cfi_offset s5, -28
870+
; RV32-NEXT: .cfi_offset s6, -32
871+
; RV32-NEXT: .cfi_offset s7, -36
872+
; RV32-NEXT: .cfi_offset s8, -40
873+
; RV32-NEXT: .cfi_offset s9, -44
874+
; RV32-NEXT: .cfi_offset s10, -48
875+
; RV32-NEXT: .cfi_offset s11, -52
876+
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
877+
; RV32-NEXT: vmv.x.s a0, v10
878+
; RV32-NEXT: vslidedown.vi v9, v10, 1
879+
; RV32-NEXT: vslidedown.vi v12, v10, 2
880+
; RV32-NEXT: vslidedown.vi v13, v10, 3
881+
; RV32-NEXT: vslidedown.vi v14, v10, 4
882+
; RV32-NEXT: vslidedown.vi v15, v10, 5
883+
; RV32-NEXT: vslidedown.vi v16, v10, 6
884+
; RV32-NEXT: vslidedown.vi v17, v10, 7
885+
; RV32-NEXT: vslidedown.vi v18, v10, 8
886+
; RV32-NEXT: vslidedown.vi v19, v10, 9
887+
; RV32-NEXT: vslidedown.vi v20, v10, 10
888+
; RV32-NEXT: vslidedown.vi v21, v10, 11
889+
; RV32-NEXT: vslidedown.vi v22, v10, 12
890+
; RV32-NEXT: vsetivli zero, 1, e8, m2, ta, ma
891+
; RV32-NEXT: vslidedown.vi v24, v10, 16
892+
; RV32-NEXT: vmv.x.s a1, v24
893+
; RV32-NEXT: vslidedown.vi v24, v10, 17
894+
; RV32-NEXT: vmv.x.s a2, v24
895+
; RV32-NEXT: vslidedown.vi v24, v10, 18
896+
; RV32-NEXT: vmv.x.s a3, v24
897+
; RV32-NEXT: vslidedown.vi v24, v10, 19
898+
; RV32-NEXT: vmv.x.s a4, v24
899+
; RV32-NEXT: vslidedown.vi v24, v10, 20
900+
; RV32-NEXT: vmv.x.s a5, v24
901+
; RV32-NEXT: vslidedown.vi v24, v10, 21
902+
; RV32-NEXT: vmv.x.s a6, v24
903+
; RV32-NEXT: vslidedown.vi v24, v10, 22
904+
; RV32-NEXT: vmv.x.s a7, v24
905+
; RV32-NEXT: vslidedown.vi v24, v10, 23
906+
; RV32-NEXT: vmv.x.s t0, v24
907+
; RV32-NEXT: vslidedown.vi v24, v10, 24
908+
; RV32-NEXT: vmv.x.s t1, v24
909+
; RV32-NEXT: vslidedown.vi v24, v10, 25
910+
; RV32-NEXT: vmv.x.s t2, v24
911+
; RV32-NEXT: vslidedown.vi v24, v10, 26
912+
; RV32-NEXT: vmv.x.s t3, v24
913+
; RV32-NEXT: vslidedown.vi v24, v10, 27
914+
; RV32-NEXT: vmv.x.s t4, v24
915+
; RV32-NEXT: vslidedown.vi v24, v10, 28
916+
; RV32-NEXT: vmv.x.s t5, v24
917+
; RV32-NEXT: vslidedown.vi v24, v10, 29
918+
; RV32-NEXT: vmv.x.s t6, v24
919+
; RV32-NEXT: vslidedown.vi v24, v10, 30
920+
; RV32-NEXT: vmv.x.s s0, v24
921+
; RV32-NEXT: vslidedown.vi v24, v10, 31
922+
; RV32-NEXT: vmv.x.s s1, v24
923+
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
924+
; RV32-NEXT: vslidedown.vi v11, v10, 13
925+
; RV32-NEXT: vslidedown.vi v23, v10, 14
926+
; RV32-NEXT: vslidedown.vi v10, v10, 15
927+
; RV32-NEXT: vmv.x.s s2, v9
928+
; RV32-NEXT: vmv.x.s s3, v12
929+
; RV32-NEXT: vmv.x.s s4, v13
930+
; RV32-NEXT: vmv.x.s s5, v14
931+
; RV32-NEXT: vmv.x.s s6, v15
932+
; RV32-NEXT: vmv.x.s s7, v16
933+
; RV32-NEXT: vmv.x.s s8, v17
934+
; RV32-NEXT: vmv.x.s s9, v18
935+
; RV32-NEXT: vmv.x.s s10, v19
936+
; RV32-NEXT: vmv.x.s s11, v20
937+
; RV32-NEXT: vmv.x.s ra, v21
938+
; RV32-NEXT: vmseq.vx v9, v8, a0
939+
; RV32-NEXT: vmv.x.s a0, v22
940+
; RV32-NEXT: vmseq.vx v12, v8, s2
941+
; RV32-NEXT: vmv.x.s s2, v11
942+
; RV32-NEXT: vmseq.vx v11, v8, s3
943+
; RV32-NEXT: vmv.x.s s3, v23
944+
; RV32-NEXT: vmseq.vx v13, v8, s4
945+
; RV32-NEXT: vmv.x.s s4, v10
946+
; RV32-NEXT: vmseq.vx v10, v8, s5
947+
; RV32-NEXT: vmor.mm v9, v9, v12
948+
; RV32-NEXT: vmseq.vx v12, v8, s6
949+
; RV32-NEXT: vmor.mm v9, v9, v11
950+
; RV32-NEXT: vmseq.vx v11, v8, s7
951+
; RV32-NEXT: vmor.mm v9, v9, v13
952+
; RV32-NEXT: vmseq.vx v13, v8, s8
953+
; RV32-NEXT: vmor.mm v9, v9, v10
954+
; RV32-NEXT: vmseq.vx v10, v8, s9
955+
; RV32-NEXT: vmor.mm v9, v9, v12
956+
; RV32-NEXT: vmseq.vx v12, v8, s10
957+
; RV32-NEXT: vmor.mm v9, v9, v11
958+
; RV32-NEXT: vmseq.vx v11, v8, s11
959+
; RV32-NEXT: vmor.mm v9, v9, v13
960+
; RV32-NEXT: vmseq.vx v13, v8, ra
961+
; RV32-NEXT: vmor.mm v9, v9, v10
962+
; RV32-NEXT: vmseq.vx v10, v8, a0
963+
; RV32-NEXT: vmor.mm v9, v9, v12
964+
; RV32-NEXT: vmseq.vx v12, v8, s2
965+
; RV32-NEXT: vmor.mm v9, v9, v11
966+
; RV32-NEXT: vmseq.vx v11, v8, s3
967+
; RV32-NEXT: vmor.mm v9, v9, v13
968+
; RV32-NEXT: vmseq.vx v13, v8, s4
969+
; RV32-NEXT: vmor.mm v9, v9, v10
970+
; RV32-NEXT: vmseq.vx v10, v8, a1
971+
; RV32-NEXT: vmor.mm v9, v9, v12
972+
; RV32-NEXT: vmseq.vx v12, v8, a2
973+
; RV32-NEXT: vmor.mm v9, v9, v11
974+
; RV32-NEXT: vmseq.vx v11, v8, a3
975+
; RV32-NEXT: vmor.mm v9, v9, v13
976+
; RV32-NEXT: vmseq.vx v13, v8, a4
977+
; RV32-NEXT: vmor.mm v9, v9, v10
978+
; RV32-NEXT: vmseq.vx v10, v8, a5
979+
; RV32-NEXT: vmor.mm v9, v9, v12
980+
; RV32-NEXT: vmseq.vx v12, v8, a6
981+
; RV32-NEXT: vmor.mm v9, v9, v11
982+
; RV32-NEXT: vmseq.vx v11, v8, a7
983+
; RV32-NEXT: vmor.mm v9, v9, v13
984+
; RV32-NEXT: vmseq.vx v13, v8, t0
985+
; RV32-NEXT: vmor.mm v9, v9, v10
986+
; RV32-NEXT: vmseq.vx v10, v8, t1
987+
; RV32-NEXT: vmor.mm v9, v9, v12
988+
; RV32-NEXT: vmseq.vx v12, v8, t2
989+
; RV32-NEXT: vmor.mm v9, v9, v11
990+
; RV32-NEXT: vmseq.vx v11, v8, t3
991+
; RV32-NEXT: vmor.mm v9, v9, v13
992+
; RV32-NEXT: vmseq.vx v13, v8, t4
993+
; RV32-NEXT: vmor.mm v9, v9, v10
994+
; RV32-NEXT: vmseq.vx v10, v8, t5
995+
; RV32-NEXT: vmor.mm v9, v9, v12
996+
; RV32-NEXT: vmseq.vx v12, v8, t6
997+
; RV32-NEXT: vmor.mm v9, v9, v11
998+
; RV32-NEXT: vmseq.vx v11, v8, s0
999+
; RV32-NEXT: vmor.mm v9, v9, v13
1000+
; RV32-NEXT: vmor.mm v9, v9, v10
1001+
; RV32-NEXT: vmor.mm v9, v9, v12
1002+
; RV32-NEXT: vmor.mm v9, v9, v11
1003+
; RV32-NEXT: vmseq.vx v8, v8, s1
1004+
; RV32-NEXT: vmor.mm v8, v9, v8
1005+
; RV32-NEXT: vmand.mm v0, v8, v0
1006+
; RV32-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
1007+
; RV32-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
1008+
; RV32-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
1009+
; RV32-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
1010+
; RV32-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
1011+
; RV32-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
1012+
; RV32-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
1013+
; RV32-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
1014+
; RV32-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
1015+
; RV32-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
1016+
; RV32-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
1017+
; RV32-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
1018+
; RV32-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
1019+
; RV32-NEXT: .cfi_restore ra
1020+
; RV32-NEXT: .cfi_restore s0
1021+
; RV32-NEXT: .cfi_restore s1
1022+
; RV32-NEXT: .cfi_restore s2
1023+
; RV32-NEXT: .cfi_restore s3
1024+
; RV32-NEXT: .cfi_restore s4
1025+
; RV32-NEXT: .cfi_restore s5
1026+
; RV32-NEXT: .cfi_restore s6
1027+
; RV32-NEXT: .cfi_restore s7
1028+
; RV32-NEXT: .cfi_restore s8
1029+
; RV32-NEXT: .cfi_restore s9
1030+
; RV32-NEXT: .cfi_restore s10
1031+
; RV32-NEXT: .cfi_restore s11
1032+
; RV32-NEXT: addi sp, sp, 64
1033+
; RV32-NEXT: .cfi_def_cfa_offset 0
1034+
; RV32-NEXT: ret
1035+
;
1036+
; RV64-LABEL: match_v16i8_v32i8:
1037+
; RV64: # %bb.0:
1038+
; RV64-NEXT: addi sp, sp, -112
1039+
; RV64-NEXT: .cfi_def_cfa_offset 112
1040+
; RV64-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
1041+
; RV64-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
1042+
; RV64-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
1043+
; RV64-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
1044+
; RV64-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
1045+
; RV64-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
1046+
; RV64-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
1047+
; RV64-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
1048+
; RV64-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
1049+
; RV64-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
1050+
; RV64-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
1051+
; RV64-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
1052+
; RV64-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
1053+
; RV64-NEXT: .cfi_offset ra, -8
1054+
; RV64-NEXT: .cfi_offset s0, -16
1055+
; RV64-NEXT: .cfi_offset s1, -24
1056+
; RV64-NEXT: .cfi_offset s2, -32
1057+
; RV64-NEXT: .cfi_offset s3, -40
1058+
; RV64-NEXT: .cfi_offset s4, -48
1059+
; RV64-NEXT: .cfi_offset s5, -56
1060+
; RV64-NEXT: .cfi_offset s6, -64
1061+
; RV64-NEXT: .cfi_offset s7, -72
1062+
; RV64-NEXT: .cfi_offset s8, -80
1063+
; RV64-NEXT: .cfi_offset s9, -88
1064+
; RV64-NEXT: .cfi_offset s10, -96
1065+
; RV64-NEXT: .cfi_offset s11, -104
1066+
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1067+
; RV64-NEXT: vmv.x.s a0, v10
1068+
; RV64-NEXT: vslidedown.vi v9, v10, 1
1069+
; RV64-NEXT: vslidedown.vi v12, v10, 2
1070+
; RV64-NEXT: vslidedown.vi v13, v10, 3
1071+
; RV64-NEXT: vslidedown.vi v14, v10, 4
1072+
; RV64-NEXT: vslidedown.vi v15, v10, 5
1073+
; RV64-NEXT: vslidedown.vi v16, v10, 6
1074+
; RV64-NEXT: vslidedown.vi v17, v10, 7
1075+
; RV64-NEXT: vslidedown.vi v18, v10, 8
1076+
; RV64-NEXT: vslidedown.vi v19, v10, 9
1077+
; RV64-NEXT: vslidedown.vi v20, v10, 10
1078+
; RV64-NEXT: vslidedown.vi v21, v10, 11
1079+
; RV64-NEXT: vslidedown.vi v22, v10, 12
1080+
; RV64-NEXT: vsetivli zero, 1, e8, m2, ta, ma
1081+
; RV64-NEXT: vslidedown.vi v24, v10, 16
1082+
; RV64-NEXT: vmv.x.s a1, v24
1083+
; RV64-NEXT: vslidedown.vi v24, v10, 17
1084+
; RV64-NEXT: vmv.x.s a2, v24
1085+
; RV64-NEXT: vslidedown.vi v24, v10, 18
1086+
; RV64-NEXT: vmv.x.s a3, v24
1087+
; RV64-NEXT: vslidedown.vi v24, v10, 19
1088+
; RV64-NEXT: vmv.x.s a4, v24
1089+
; RV64-NEXT: vslidedown.vi v24, v10, 20
1090+
; RV64-NEXT: vmv.x.s a5, v24
1091+
; RV64-NEXT: vslidedown.vi v24, v10, 21
1092+
; RV64-NEXT: vmv.x.s a6, v24
1093+
; RV64-NEXT: vslidedown.vi v24, v10, 22
1094+
; RV64-NEXT: vmv.x.s a7, v24
1095+
; RV64-NEXT: vslidedown.vi v24, v10, 23
1096+
; RV64-NEXT: vmv.x.s t0, v24
1097+
; RV64-NEXT: vslidedown.vi v24, v10, 24
1098+
; RV64-NEXT: vmv.x.s t1, v24
1099+
; RV64-NEXT: vslidedown.vi v24, v10, 25
1100+
; RV64-NEXT: vmv.x.s t2, v24
1101+
; RV64-NEXT: vslidedown.vi v24, v10, 26
1102+
; RV64-NEXT: vmv.x.s t3, v24
1103+
; RV64-NEXT: vslidedown.vi v24, v10, 27
1104+
; RV64-NEXT: vmv.x.s t4, v24
1105+
; RV64-NEXT: vslidedown.vi v24, v10, 28
1106+
; RV64-NEXT: vmv.x.s t5, v24
1107+
; RV64-NEXT: vslidedown.vi v24, v10, 29
1108+
; RV64-NEXT: vmv.x.s t6, v24
1109+
; RV64-NEXT: vslidedown.vi v24, v10, 30
1110+
; RV64-NEXT: vmv.x.s s0, v24
1111+
; RV64-NEXT: vslidedown.vi v24, v10, 31
1112+
; RV64-NEXT: vmv.x.s s1, v24
1113+
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1114+
; RV64-NEXT: vslidedown.vi v11, v10, 13
1115+
; RV64-NEXT: vslidedown.vi v23, v10, 14
1116+
; RV64-NEXT: vslidedown.vi v10, v10, 15
1117+
; RV64-NEXT: vmv.x.s s2, v9
1118+
; RV64-NEXT: vmv.x.s s3, v12
1119+
; RV64-NEXT: vmv.x.s s4, v13
1120+
; RV64-NEXT: vmv.x.s s5, v14
1121+
; RV64-NEXT: vmv.x.s s6, v15
1122+
; RV64-NEXT: vmv.x.s s7, v16
1123+
; RV64-NEXT: vmv.x.s s8, v17
1124+
; RV64-NEXT: vmv.x.s s9, v18
1125+
; RV64-NEXT: vmv.x.s s10, v19
1126+
; RV64-NEXT: vmv.x.s s11, v20
1127+
; RV64-NEXT: vmv.x.s ra, v21
1128+
; RV64-NEXT: vmseq.vx v9, v8, a0
1129+
; RV64-NEXT: vmv.x.s a0, v22
1130+
; RV64-NEXT: vmseq.vx v12, v8, s2
1131+
; RV64-NEXT: vmv.x.s s2, v11
1132+
; RV64-NEXT: vmseq.vx v11, v8, s3
1133+
; RV64-NEXT: vmv.x.s s3, v23
1134+
; RV64-NEXT: vmseq.vx v13, v8, s4
1135+
; RV64-NEXT: vmv.x.s s4, v10
1136+
; RV64-NEXT: vmseq.vx v10, v8, s5
1137+
; RV64-NEXT: vmor.mm v9, v9, v12
1138+
; RV64-NEXT: vmseq.vx v12, v8, s6
1139+
; RV64-NEXT: vmor.mm v9, v9, v11
1140+
; RV64-NEXT: vmseq.vx v11, v8, s7
1141+
; RV64-NEXT: vmor.mm v9, v9, v13
1142+
; RV64-NEXT: vmseq.vx v13, v8, s8
1143+
; RV64-NEXT: vmor.mm v9, v9, v10
1144+
; RV64-NEXT: vmseq.vx v10, v8, s9
1145+
; RV64-NEXT: vmor.mm v9, v9, v12
1146+
; RV64-NEXT: vmseq.vx v12, v8, s10
1147+
; RV64-NEXT: vmor.mm v9, v9, v11
1148+
; RV64-NEXT: vmseq.vx v11, v8, s11
1149+
; RV64-NEXT: vmor.mm v9, v9, v13
1150+
; RV64-NEXT: vmseq.vx v13, v8, ra
1151+
; RV64-NEXT: vmor.mm v9, v9, v10
1152+
; RV64-NEXT: vmseq.vx v10, v8, a0
1153+
; RV64-NEXT: vmor.mm v9, v9, v12
1154+
; RV64-NEXT: vmseq.vx v12, v8, s2
1155+
; RV64-NEXT: vmor.mm v9, v9, v11
1156+
; RV64-NEXT: vmseq.vx v11, v8, s3
1157+
; RV64-NEXT: vmor.mm v9, v9, v13
1158+
; RV64-NEXT: vmseq.vx v13, v8, s4
1159+
; RV64-NEXT: vmor.mm v9, v9, v10
1160+
; RV64-NEXT: vmseq.vx v10, v8, a1
1161+
; RV64-NEXT: vmor.mm v9, v9, v12
1162+
; RV64-NEXT: vmseq.vx v12, v8, a2
1163+
; RV64-NEXT: vmor.mm v9, v9, v11
1164+
; RV64-NEXT: vmseq.vx v11, v8, a3
1165+
; RV64-NEXT: vmor.mm v9, v9, v13
1166+
; RV64-NEXT: vmseq.vx v13, v8, a4
1167+
; RV64-NEXT: vmor.mm v9, v9, v10
1168+
; RV64-NEXT: vmseq.vx v10, v8, a5
1169+
; RV64-NEXT: vmor.mm v9, v9, v12
1170+
; RV64-NEXT: vmseq.vx v12, v8, a6
1171+
; RV64-NEXT: vmor.mm v9, v9, v11
1172+
; RV64-NEXT: vmseq.vx v11, v8, a7
1173+
; RV64-NEXT: vmor.mm v9, v9, v13
1174+
; RV64-NEXT: vmseq.vx v13, v8, t0
1175+
; RV64-NEXT: vmor.mm v9, v9, v10
1176+
; RV64-NEXT: vmseq.vx v10, v8, t1
1177+
; RV64-NEXT: vmor.mm v9, v9, v12
1178+
; RV64-NEXT: vmseq.vx v12, v8, t2
1179+
; RV64-NEXT: vmor.mm v9, v9, v11
1180+
; RV64-NEXT: vmseq.vx v11, v8, t3
1181+
; RV64-NEXT: vmor.mm v9, v9, v13
1182+
; RV64-NEXT: vmseq.vx v13, v8, t4
1183+
; RV64-NEXT: vmor.mm v9, v9, v10
1184+
; RV64-NEXT: vmseq.vx v10, v8, t5
1185+
; RV64-NEXT: vmor.mm v9, v9, v12
1186+
; RV64-NEXT: vmseq.vx v12, v8, t6
1187+
; RV64-NEXT: vmor.mm v9, v9, v11
1188+
; RV64-NEXT: vmseq.vx v11, v8, s0
1189+
; RV64-NEXT: vmor.mm v9, v9, v13
1190+
; RV64-NEXT: vmor.mm v9, v9, v10
1191+
; RV64-NEXT: vmor.mm v9, v9, v12
1192+
; RV64-NEXT: vmor.mm v9, v9, v11
1193+
; RV64-NEXT: vmseq.vx v8, v8, s1
1194+
; RV64-NEXT: vmor.mm v8, v9, v8
1195+
; RV64-NEXT: vmand.mm v0, v8, v0
1196+
; RV64-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
1197+
; RV64-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
1198+
; RV64-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
1199+
; RV64-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
1200+
; RV64-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
1201+
; RV64-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
1202+
; RV64-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
1203+
; RV64-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
1204+
; RV64-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
1205+
; RV64-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
1206+
; RV64-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
1207+
; RV64-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
1208+
; RV64-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
1209+
; RV64-NEXT: .cfi_restore ra
1210+
; RV64-NEXT: .cfi_restore s0
1211+
; RV64-NEXT: .cfi_restore s1
1212+
; RV64-NEXT: .cfi_restore s2
1213+
; RV64-NEXT: .cfi_restore s3
1214+
; RV64-NEXT: .cfi_restore s4
1215+
; RV64-NEXT: .cfi_restore s5
1216+
; RV64-NEXT: .cfi_restore s6
1217+
; RV64-NEXT: .cfi_restore s7
1218+
; RV64-NEXT: .cfi_restore s8
1219+
; RV64-NEXT: .cfi_restore s9
1220+
; RV64-NEXT: .cfi_restore s10
1221+
; RV64-NEXT: .cfi_restore s11
1222+
; RV64-NEXT: addi sp, sp, 112
1223+
; RV64-NEXT: .cfi_def_cfa_offset 0
1224+
; RV64-NEXT: ret
1225+
%r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <32 x i8> %op2, <16 x i1> %mask)
1226+
ret <16 x i1> %r
1227+
}
1228+
8451229
define <vscale x 4 x i1> @match_nxv4xi32_v4i32(<vscale x 4 x i32> %op1, <4 x i32> %op2, <vscale x 4 x i1> %mask) {
8461230
; CHECK-LABEL: match_nxv4xi32_v4i32:
8471231
; CHECK: # %bb.0:

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