[lldb][elf-core][ARM] Add support for VFP registers (#155956)

This patch loads values of the VFP registers from the NT_ARM_VFP note.

Note that a CORE/NT_FPREGSET note is typically present in core dump
files and is used to store the FPA registers. The FPA unit is rare and
obsolete; however, Linux creates the note even if the unit is absent.

Author: igorkudrin

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp

@@ -23,6 +23,10 @@ RegisterContextCorePOSIX_arm::RegisterContextCorePOSIX_arm(
                                                   gpregset.GetByteSize());
   m_gpr.SetData(m_gpr_buffer);
   m_gpr.SetByteOrder(gpregset.GetByteOrder());
+
+  const llvm::Triple &target_triple =
+      m_register_info_up->GetTargetArchitecture().GetTriple();
+  m_fpr = getRegset(notes, target_triple, ARM_VFP_Desc);
 }
 
 RegisterContextCorePOSIX_arm::~RegisterContextCorePOSIX_arm() = default;
@@ -43,14 +47,25 @@ bool RegisterContextCorePOSIX_arm::WriteFPR() {
 
 bool RegisterContextCorePOSIX_arm::ReadRegister(const RegisterInfo *reg_info,
                                                 RegisterValue &value) {
-  lldb::offset_t offset = reg_info->byte_offset;
-  if (offset + reg_info->byte_size <= GetGPRSize()) {
-    uint64_t v = m_gpr.GetMaxU64(&offset, reg_info->byte_size);
-    if (offset == reg_info->byte_offset + reg_info->byte_size) {
-      value = v;
-      return true;
+  const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+  if (reg == LLDB_INVALID_REGNUM)
+    return false;
+
+  if (IsGPR(reg)) {
+    lldb::offset_t offset = reg_info->byte_offset;
+    if (m_gpr.ValidOffsetForDataOfSize(offset, reg_info->byte_size)) {
+      value = m_gpr.GetMaxU64(&offset, reg_info->byte_size);
+      return offset == reg_info->byte_offset + reg_info->byte_size;
     }
+  } else if (IsFPR(reg)) {
+    assert(reg_info->byte_offset >= GetGPRSize());
+    lldb::offset_t offset = reg_info->byte_offset - GetGPRSize();
+    if (m_fpr.ValidOffsetForDataOfSize(offset, reg_info->byte_size))
+      return value
+          .SetValueFromData(*reg_info, m_fpr, offset, /*partial_data_ok=*/false)
+          .Success();
   }
+
   return false;
 }
 

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h

@@ -48,6 +48,7 @@ class RegisterContextCorePOSIX_arm : public RegisterContextPOSIX_arm {
 private:
   lldb::DataBufferSP m_gpr_buffer;
   lldb_private::DataExtractor m_gpr;
+  lldb_private::DataExtractor m_fpr;
 };
 
 #endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_ARM_H

lldb/source/Plugins/Process/elf-core/RegisterUtilities.h

@@ -152,6 +152,11 @@ constexpr RegsetDesc AARCH64_GCS_Desc[] = {
     {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_GCS},
 };
 
+constexpr RegsetDesc ARM_VFP_Desc[] = {
+    {llvm::Triple::FreeBSD, llvm::Triple::arm, llvm::ELF::NT_ARM_VFP},
+    {llvm::Triple::Linux, llvm::Triple::arm, llvm::ELF::NT_ARM_VFP},
+};
+
 constexpr RegsetDesc PPC_VMX_Desc[] = {
     {llvm::Triple::FreeBSD, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VMX},
     {llvm::Triple::Linux, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VMX},

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

@@ -696,6 +696,43 @@ def test_arm_core(self):
 
         self.expect("register read --all")
 
+    @skipIfLLVMTargetMissing("ARM")
+    def test_arm_core_vfp(self):
+        # check reading VFP registers
+        target = self.dbg.CreateTarget(None)
+        self.assertTrue(target, VALID_TARGET)
+        process = target.LoadCore("linux-arm-vfp.core")
+
+        values = {
+            "d0": "0.5",
+            "d1": "1.5",
+            "d14": "14.5",
+            "d15": "15.5",
+            "s4": "4.5",
+            "s5": "5.5",
+            "s6": "6.5",
+            "s7": "7.5",
+            "fpscr": "0x20000000",
+            # s0 and s1 overlap d0, s2 and s3 overlap d1 and so on. Therefore,
+            # the following values are not as neat as those in the explicitly
+            # set registers.
+            "s0": "0",
+            "s1": "1.75",
+            "s2": "0",
+            "s3": "1.9375",
+            "s28": "0",
+            "s29": "2.703125",
+            "s30": "0",
+            "s31": "2.734375",
+        }
+        for regname, value in values.items():
+            self.expect(
+                "register read {}".format(regname),
+                substrs=["{} = {}".format(regname, value)],
+            )
+
+        self.expect("register read --all")
+
     @skipIfLLVMTargetMissing("RISCV")
     def test_riscv64_regs_gpr_fpr(self):
         # check basic registers using 64 bit RISC-V core file

lldb/test/API/functionalities/postmortem/elf-core/linux-arm-vfp.c

@@ -0,0 +1,24 @@
+// linux-arm-vfp.core was generated with:
+// > gcc-12 -march=armv7+fp -nostdlib -static -Wl,--build-id=none \
+//   linux-arm-vfp.c -o linux-arm-vfp.out
+// > ulimit -c 1000
+// > ulimit -s 8
+// > env -i ./linux-arm-vfp.out
+
+static void foo(char *boom) {
+  asm volatile(R"(
+    vmov.f64  d0,  #0.5
+    vmov.f64  d1,  #1.5
+    vmov.f64  d14, #14.5
+    vmov.f64  d15, #15.5
+    vmov.f32  s4,  #4.5
+    vmov.f32  s5,  #5.5
+    vmov.f32  s6,  #6.5
+    vmov.f32  s7,  #7.5
+    vcmp.f32  s7,  s6
+  )");
+
+  *boom = 47;
+}
+
+void _start(void) { foo(0); }