fix vector types

Author: frasercrmck

llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp

@@ -441,11 +441,13 @@ bool SPIRVLegalizerInfo::legalizeIsFPClass(
     if (!Ty.isFixedVector())
       return assignSPIRVTy(MIRBuilder.buildConstant(Ty, C));
     auto ScalarC = MIRBuilder.buildConstant(Ty.getScalarType(), C);
-    SPIRVType *SPIRVIntEltTy =
-        GR->getOrCreateSPIRVType(LLVMIntTy->getScalarType(), MIRBuilder,
-                                 SPIRV::AccessQualifier::ReadWrite,
-                                 /*EmitIR*/ true);
-    GR->assignSPIRVTypeToVReg(SPIRVIntEltTy, ScalarC.getReg(0), MF);
+    assert((Ty == IntTy || Ty == DstTyCopy) &&
+           "Unexpected LLT type while lowering constant for G_IS_FPCLASS");
+    SPIRVType *VecEltTy = GR->getOrCreateSPIRVType(
+        (Ty == IntTy ? LLVMIntTy : LLVMDstTy)->getScalarType(), MIRBuilder,
+        SPIRV::AccessQualifier::ReadWrite,
+        /*EmitIR*/ true);
+    GR->assignSPIRVTypeToVReg(VecEltTy, ScalarC.getReg(0), MF);
     return assignSPIRVTy(MIRBuilder.buildSplatBuildVector(Ty, ScalarC));
   };
 

llvm/test/CodeGen/SPIRV/llvm-intrinsics/is_fpclass.ll

@@ -33,7 +33,7 @@
 ; CHECK-DAG: %[[#InfFP64:]] = OpConstant %[[#I64Ty]] 9218868437227405312
 ; CHECK-DAG: %[[#NegInfFP64:]] = OpConstant %[[#I64Ty]] 18442240474082181120
 
-; CHECK-DAG: %[[#FalseV4:]] = OpConstantComposite %[[#V4BoolTy]] %[[#Zero]] %[[#Zero]] %[[#Zero]] %[[#Zero]]
+; CHECK-DAG: %[[#FalseV4:]] = OpConstantComposite %[[#V4BoolTy]] %[[#False]] %[[#False]] %[[#False]] %[[#False]]
 ; CHECK-DAG: %[[#ValueMaskV4:]] = OpConstantComposite %[[#V4I32Ty]] %[[#ValueMask]] %[[#ValueMask]] %[[#ValueMask]] %[[#ValueMask]]
 ; CHECK-DAG: %[[#InfV4:]] = OpConstantComposite %[[#V4I32Ty]] %[[#Inf]] %[[#Inf]] %[[#Inf]] %[[#Inf]]
 ; CHECK-DAG: %[[#InfWithQnanBitV4:]] = OpConstantComposite %[[#V4I32Ty]] %[[#InfWithQnanBit]] %[[#InfWithQnanBit]] %[[#InfWithQnanBit]] %[[#InfWithQnanBit]]