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[RISCV] Add coverage for select C, C1, C2 where (C1-C2)*[0,1] is cheap
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+319
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‎llvm/test/CodeGen/RISCV/select.ll‎

Lines changed: 319 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1819,8 +1819,8 @@ define i32 @select_cst5(i1 zeroext %cond) {
18191819
ret i32 %ret
18201820
}
18211821

1822-
define i32 @select_cst6(i1 zeroext %cond) {
1823-
; RV32IM-LABEL: select_cst6:
1822+
define i32 @select_cst5_invert(i1 zeroext %cond) {
1823+
; RV32IM-LABEL: select_cst5_invert:
18241824
; RV32IM: # %bb.0:
18251825
; RV32IM-NEXT: bnez a0, .LBB48_2
18261826
; RV32IM-NEXT: # %bb.1:
@@ -1831,7 +1831,7 @@ define i32 @select_cst6(i1 zeroext %cond) {
18311831
; RV32IM-NEXT: addi a0, a0, -2047
18321832
; RV32IM-NEXT: ret
18331833
;
1834-
; RV64IM-LABEL: select_cst6:
1834+
; RV64IM-LABEL: select_cst5_invert:
18351835
; RV64IM: # %bb.0:
18361836
; RV64IM-NEXT: bnez a0, .LBB48_2
18371837
; RV64IM-NEXT: # %bb.1:
@@ -1842,14 +1842,14 @@ define i32 @select_cst6(i1 zeroext %cond) {
18421842
; RV64IM-NEXT: addiw a0, a0, -2047
18431843
; RV64IM-NEXT: ret
18441844
;
1845-
; RV64IMXVTCONDOPS-LABEL: select_cst6:
1845+
; RV64IMXVTCONDOPS-LABEL: select_cst5_invert:
18461846
; RV64IMXVTCONDOPS: # %bb.0:
18471847
; RV64IMXVTCONDOPS-NEXT: li a1, 2
18481848
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0
18491849
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 2047
18501850
; RV64IMXVTCONDOPS-NEXT: ret
18511851
;
1852-
; CHECKZICOND-LABEL: select_cst6:
1852+
; CHECKZICOND-LABEL: select_cst5_invert:
18531853
; CHECKZICOND: # %bb.0:
18541854
; CHECKZICOND-NEXT: li a1, 2
18551855
; CHECKZICOND-NEXT: czero.eqz a0, a1, a0
@@ -1859,26 +1859,332 @@ define i32 @select_cst6(i1 zeroext %cond) {
18591859
ret i32 %ret
18601860
}
18611861

1862+
define i32 @select_cst_diff2(i1 zeroext %cond) {
1863+
; RV32IM-LABEL: select_cst_diff2:
1864+
; RV32IM: # %bb.0:
1865+
; RV32IM-NEXT: mv a1, a0
1866+
; RV32IM-NEXT: li a0, 120
1867+
; RV32IM-NEXT: bnez a1, .LBB49_2
1868+
; RV32IM-NEXT: # %bb.1:
1869+
; RV32IM-NEXT: li a0, 122
1870+
; RV32IM-NEXT: .LBB49_2:
1871+
; RV32IM-NEXT: ret
1872+
;
1873+
; RV64IM-LABEL: select_cst_diff2:
1874+
; RV64IM: # %bb.0:
1875+
; RV64IM-NEXT: mv a1, a0
1876+
; RV64IM-NEXT: li a0, 120
1877+
; RV64IM-NEXT: bnez a1, .LBB49_2
1878+
; RV64IM-NEXT: # %bb.1:
1879+
; RV64IM-NEXT: li a0, 122
1880+
; RV64IM-NEXT: .LBB49_2:
1881+
; RV64IM-NEXT: ret
1882+
;
1883+
; RV64IMXVTCONDOPS-LABEL: select_cst_diff2:
1884+
; RV64IMXVTCONDOPS: # %bb.0:
1885+
; RV64IMXVTCONDOPS-NEXT: li a1, 2
1886+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1887+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 120
1888+
; RV64IMXVTCONDOPS-NEXT: ret
1889+
;
1890+
; CHECKZICOND-LABEL: select_cst_diff2:
1891+
; CHECKZICOND: # %bb.0:
1892+
; CHECKZICOND-NEXT: li a1, 2
1893+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
1894+
; CHECKZICOND-NEXT: addi a0, a0, 120
1895+
; CHECKZICOND-NEXT: ret
1896+
%ret = select i1 %cond, i32 120, i32 122
1897+
ret i32 %ret
1898+
}
1899+
1900+
define i32 @select_cst_diff2_invert(i1 zeroext %cond) {
1901+
; RV32IM-LABEL: select_cst_diff2_invert:
1902+
; RV32IM: # %bb.0:
1903+
; RV32IM-NEXT: mv a1, a0
1904+
; RV32IM-NEXT: li a0, 122
1905+
; RV32IM-NEXT: bnez a1, .LBB50_2
1906+
; RV32IM-NEXT: # %bb.1:
1907+
; RV32IM-NEXT: li a0, 120
1908+
; RV32IM-NEXT: .LBB50_2:
1909+
; RV32IM-NEXT: ret
1910+
;
1911+
; RV64IM-LABEL: select_cst_diff2_invert:
1912+
; RV64IM: # %bb.0:
1913+
; RV64IM-NEXT: mv a1, a0
1914+
; RV64IM-NEXT: li a0, 122
1915+
; RV64IM-NEXT: bnez a1, .LBB50_2
1916+
; RV64IM-NEXT: # %bb.1:
1917+
; RV64IM-NEXT: li a0, 120
1918+
; RV64IM-NEXT: .LBB50_2:
1919+
; RV64IM-NEXT: ret
1920+
;
1921+
; RV64IMXVTCONDOPS-LABEL: select_cst_diff2_invert:
1922+
; RV64IMXVTCONDOPS: # %bb.0:
1923+
; RV64IMXVTCONDOPS-NEXT: li a1, -2
1924+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1925+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 122
1926+
; RV64IMXVTCONDOPS-NEXT: ret
1927+
;
1928+
; CHECKZICOND-LABEL: select_cst_diff2_invert:
1929+
; CHECKZICOND: # %bb.0:
1930+
; CHECKZICOND-NEXT: li a1, -2
1931+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
1932+
; CHECKZICOND-NEXT: addi a0, a0, 122
1933+
; CHECKZICOND-NEXT: ret
1934+
%ret = select i1 %cond, i32 122, i32 120
1935+
ret i32 %ret
1936+
}
1937+
1938+
define i32 @select_cst_diff4(i1 zeroext %cond) {
1939+
; RV32IM-LABEL: select_cst_diff4:
1940+
; RV32IM: # %bb.0:
1941+
; RV32IM-NEXT: mv a1, a0
1942+
; RV32IM-NEXT: li a0, 10
1943+
; RV32IM-NEXT: bnez a1, .LBB51_2
1944+
; RV32IM-NEXT: # %bb.1:
1945+
; RV32IM-NEXT: li a0, 6
1946+
; RV32IM-NEXT: .LBB51_2:
1947+
; RV32IM-NEXT: ret
1948+
;
1949+
; RV64IM-LABEL: select_cst_diff4:
1950+
; RV64IM: # %bb.0:
1951+
; RV64IM-NEXT: mv a1, a0
1952+
; RV64IM-NEXT: li a0, 10
1953+
; RV64IM-NEXT: bnez a1, .LBB51_2
1954+
; RV64IM-NEXT: # %bb.1:
1955+
; RV64IM-NEXT: li a0, 6
1956+
; RV64IM-NEXT: .LBB51_2:
1957+
; RV64IM-NEXT: ret
1958+
;
1959+
; RV64IMXVTCONDOPS-LABEL: select_cst_diff4:
1960+
; RV64IMXVTCONDOPS: # %bb.0:
1961+
; RV64IMXVTCONDOPS-NEXT: li a1, -4
1962+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1963+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 10
1964+
; RV64IMXVTCONDOPS-NEXT: ret
1965+
;
1966+
; CHECKZICOND-LABEL: select_cst_diff4:
1967+
; CHECKZICOND: # %bb.0:
1968+
; CHECKZICOND-NEXT: li a1, -4
1969+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
1970+
; CHECKZICOND-NEXT: addi a0, a0, 10
1971+
; CHECKZICOND-NEXT: ret
1972+
%ret = select i1 %cond, i32 10, i32 6
1973+
ret i32 %ret
1974+
}
1975+
1976+
define i32 @select_cst_diff4_invert(i1 zeroext %cond) {
1977+
; RV32IM-LABEL: select_cst_diff4_invert:
1978+
; RV32IM: # %bb.0:
1979+
; RV32IM-NEXT: mv a1, a0
1980+
; RV32IM-NEXT: li a0, 6
1981+
; RV32IM-NEXT: bnez a1, .LBB52_2
1982+
; RV32IM-NEXT: # %bb.1:
1983+
; RV32IM-NEXT: li a0, 10
1984+
; RV32IM-NEXT: .LBB52_2:
1985+
; RV32IM-NEXT: ret
1986+
;
1987+
; RV64IM-LABEL: select_cst_diff4_invert:
1988+
; RV64IM: # %bb.0:
1989+
; RV64IM-NEXT: mv a1, a0
1990+
; RV64IM-NEXT: li a0, 6
1991+
; RV64IM-NEXT: bnez a1, .LBB52_2
1992+
; RV64IM-NEXT: # %bb.1:
1993+
; RV64IM-NEXT: li a0, 10
1994+
; RV64IM-NEXT: .LBB52_2:
1995+
; RV64IM-NEXT: ret
1996+
;
1997+
; RV64IMXVTCONDOPS-LABEL: select_cst_diff4_invert:
1998+
; RV64IMXVTCONDOPS: # %bb.0:
1999+
; RV64IMXVTCONDOPS-NEXT: li a1, 4
2000+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
2001+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 6
2002+
; RV64IMXVTCONDOPS-NEXT: ret
2003+
;
2004+
; CHECKZICOND-LABEL: select_cst_diff4_invert:
2005+
; CHECKZICOND: # %bb.0:
2006+
; CHECKZICOND-NEXT: li a1, 4
2007+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
2008+
; CHECKZICOND-NEXT: addi a0, a0, 6
2009+
; CHECKZICOND-NEXT: ret
2010+
%ret = select i1 %cond, i32 6, i32 10
2011+
ret i32 %ret
2012+
}
2013+
2014+
define i32 @select_cst_diff8(i1 zeroext %cond) {
2015+
; RV32IM-LABEL: select_cst_diff8:
2016+
; RV32IM: # %bb.0:
2017+
; RV32IM-NEXT: mv a1, a0
2018+
; RV32IM-NEXT: li a0, 14
2019+
; RV32IM-NEXT: bnez a1, .LBB53_2
2020+
; RV32IM-NEXT: # %bb.1:
2021+
; RV32IM-NEXT: li a0, 6
2022+
; RV32IM-NEXT: .LBB53_2:
2023+
; RV32IM-NEXT: ret
2024+
;
2025+
; RV64IM-LABEL: select_cst_diff8:
2026+
; RV64IM: # %bb.0:
2027+
; RV64IM-NEXT: mv a1, a0
2028+
; RV64IM-NEXT: li a0, 14
2029+
; RV64IM-NEXT: bnez a1, .LBB53_2
2030+
; RV64IM-NEXT: # %bb.1:
2031+
; RV64IM-NEXT: li a0, 6
2032+
; RV64IM-NEXT: .LBB53_2:
2033+
; RV64IM-NEXT: ret
2034+
;
2035+
; RV64IMXVTCONDOPS-LABEL: select_cst_diff8:
2036+
; RV64IMXVTCONDOPS: # %bb.0:
2037+
; RV64IMXVTCONDOPS-NEXT: li a1, -8
2038+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
2039+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 14
2040+
; RV64IMXVTCONDOPS-NEXT: ret
2041+
;
2042+
; CHECKZICOND-LABEL: select_cst_diff8:
2043+
; CHECKZICOND: # %bb.0:
2044+
; CHECKZICOND-NEXT: li a1, -8
2045+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
2046+
; CHECKZICOND-NEXT: addi a0, a0, 14
2047+
; CHECKZICOND-NEXT: ret
2048+
%ret = select i1 %cond, i32 14, i32 6
2049+
ret i32 %ret
2050+
}
2051+
2052+
define i32 @select_cst_diff8_invert(i1 zeroext %cond) {
2053+
; RV32IM-LABEL: select_cst_diff8_invert:
2054+
; RV32IM: # %bb.0:
2055+
; RV32IM-NEXT: mv a1, a0
2056+
; RV32IM-NEXT: li a0, 6
2057+
; RV32IM-NEXT: bnez a1, .LBB54_2
2058+
; RV32IM-NEXT: # %bb.1:
2059+
; RV32IM-NEXT: li a0, 14
2060+
; RV32IM-NEXT: .LBB54_2:
2061+
; RV32IM-NEXT: ret
2062+
;
2063+
; RV64IM-LABEL: select_cst_diff8_invert:
2064+
; RV64IM: # %bb.0:
2065+
; RV64IM-NEXT: mv a1, a0
2066+
; RV64IM-NEXT: li a0, 6
2067+
; RV64IM-NEXT: bnez a1, .LBB54_2
2068+
; RV64IM-NEXT: # %bb.1:
2069+
; RV64IM-NEXT: li a0, 14
2070+
; RV64IM-NEXT: .LBB54_2:
2071+
; RV64IM-NEXT: ret
2072+
;
2073+
; RV64IMXVTCONDOPS-LABEL: select_cst_diff8_invert:
2074+
; RV64IMXVTCONDOPS: # %bb.0:
2075+
; RV64IMXVTCONDOPS-NEXT: li a1, 8
2076+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
2077+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 6
2078+
; RV64IMXVTCONDOPS-NEXT: ret
2079+
;
2080+
; CHECKZICOND-LABEL: select_cst_diff8_invert:
2081+
; CHECKZICOND: # %bb.0:
2082+
; CHECKZICOND-NEXT: li a1, 8
2083+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
2084+
; CHECKZICOND-NEXT: addi a0, a0, 6
2085+
; CHECKZICOND-NEXT: ret
2086+
%ret = select i1 %cond, i32 6, i32 14
2087+
ret i32 %ret
2088+
}
2089+
2090+
2091+
define i32 @select_cst_diff1024(i1 zeroext %cond) {
2092+
; RV32IM-LABEL: select_cst_diff1024:
2093+
; RV32IM: # %bb.0:
2094+
; RV32IM-NEXT: mv a1, a0
2095+
; RV32IM-NEXT: li a0, 1030
2096+
; RV32IM-NEXT: bnez a1, .LBB55_2
2097+
; RV32IM-NEXT: # %bb.1:
2098+
; RV32IM-NEXT: li a0, 6
2099+
; RV32IM-NEXT: .LBB55_2:
2100+
; RV32IM-NEXT: ret
2101+
;
2102+
; RV64IM-LABEL: select_cst_diff1024:
2103+
; RV64IM: # %bb.0:
2104+
; RV64IM-NEXT: mv a1, a0
2105+
; RV64IM-NEXT: li a0, 1030
2106+
; RV64IM-NEXT: bnez a1, .LBB55_2
2107+
; RV64IM-NEXT: # %bb.1:
2108+
; RV64IM-NEXT: li a0, 6
2109+
; RV64IM-NEXT: .LBB55_2:
2110+
; RV64IM-NEXT: ret
2111+
;
2112+
; RV64IMXVTCONDOPS-LABEL: select_cst_diff1024:
2113+
; RV64IMXVTCONDOPS: # %bb.0:
2114+
; RV64IMXVTCONDOPS-NEXT: li a1, -1024
2115+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
2116+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 1030
2117+
; RV64IMXVTCONDOPS-NEXT: ret
2118+
;
2119+
; CHECKZICOND-LABEL: select_cst_diff1024:
2120+
; CHECKZICOND: # %bb.0:
2121+
; CHECKZICOND-NEXT: li a1, -1024
2122+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
2123+
; CHECKZICOND-NEXT: addi a0, a0, 1030
2124+
; CHECKZICOND-NEXT: ret
2125+
%ret = select i1 %cond, i32 1030, i32 6
2126+
ret i32 %ret
2127+
}
2128+
2129+
define i32 @select_cst_diff1024_invert(i1 zeroext %cond) {
2130+
; RV32IM-LABEL: select_cst_diff1024_invert:
2131+
; RV32IM: # %bb.0:
2132+
; RV32IM-NEXT: mv a1, a0
2133+
; RV32IM-NEXT: li a0, 6
2134+
; RV32IM-NEXT: bnez a1, .LBB56_2
2135+
; RV32IM-NEXT: # %bb.1:
2136+
; RV32IM-NEXT: li a0, 1030
2137+
; RV32IM-NEXT: .LBB56_2:
2138+
; RV32IM-NEXT: ret
2139+
;
2140+
; RV64IM-LABEL: select_cst_diff1024_invert:
2141+
; RV64IM: # %bb.0:
2142+
; RV64IM-NEXT: mv a1, a0
2143+
; RV64IM-NEXT: li a0, 6
2144+
; RV64IM-NEXT: bnez a1, .LBB56_2
2145+
; RV64IM-NEXT: # %bb.1:
2146+
; RV64IM-NEXT: li a0, 1030
2147+
; RV64IM-NEXT: .LBB56_2:
2148+
; RV64IM-NEXT: ret
2149+
;
2150+
; RV64IMXVTCONDOPS-LABEL: select_cst_diff1024_invert:
2151+
; RV64IMXVTCONDOPS: # %bb.0:
2152+
; RV64IMXVTCONDOPS-NEXT: li a1, 1024
2153+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
2154+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 6
2155+
; RV64IMXVTCONDOPS-NEXT: ret
2156+
;
2157+
; CHECKZICOND-LABEL: select_cst_diff1024_invert:
2158+
; CHECKZICOND: # %bb.0:
2159+
; CHECKZICOND-NEXT: li a1, 1024
2160+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
2161+
; CHECKZICOND-NEXT: addi a0, a0, 6
2162+
; CHECKZICOND-NEXT: ret
2163+
%ret = select i1 %cond, i32 6, i32 1030
2164+
ret i32 %ret
2165+
}
2166+
2167+
18622168
@select_redundant_czero_eqz_data = global i32 0, align 4
18632169

18642170
define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
18652171
; RV32IM-LABEL: select_redundant_czero_eqz1:
18662172
; RV32IM: # %bb.0: # %entry
1867-
; RV32IM-NEXT: bnez a0, .LBB49_2
2173+
; RV32IM-NEXT: bnez a0, .LBB57_2
18682174
; RV32IM-NEXT: # %bb.1:
18692175
; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)
18702176
; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)
1871-
; RV32IM-NEXT: .LBB49_2: # %entry
2177+
; RV32IM-NEXT: .LBB57_2: # %entry
18722178
; RV32IM-NEXT: sw a0, 0(a1)
18732179
; RV32IM-NEXT: ret
18742180
;
18752181
; RV64IM-LABEL: select_redundant_czero_eqz1:
18762182
; RV64IM: # %bb.0: # %entry
1877-
; RV64IM-NEXT: bnez a0, .LBB49_2
2183+
; RV64IM-NEXT: bnez a0, .LBB57_2
18782184
; RV64IM-NEXT: # %bb.1:
18792185
; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)
18802186
; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)
1881-
; RV64IM-NEXT: .LBB49_2: # %entry
2187+
; RV64IM-NEXT: .LBB57_2: # %entry
18822188
; RV64IM-NEXT: sd a0, 0(a1)
18832189
; RV64IM-NEXT: ret
18842190
;
@@ -1918,21 +2224,21 @@ entry:
19182224
define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
19192225
; RV32IM-LABEL: select_redundant_czero_eqz2:
19202226
; RV32IM: # %bb.0: # %entry
1921-
; RV32IM-NEXT: bnez a0, .LBB50_2
2227+
; RV32IM-NEXT: bnez a0, .LBB58_2
19222228
; RV32IM-NEXT: # %bb.1: # %entry
19232229
; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)
19242230
; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)
1925-
; RV32IM-NEXT: .LBB50_2: # %entry
2231+
; RV32IM-NEXT: .LBB58_2: # %entry
19262232
; RV32IM-NEXT: sw a0, 0(a1)
19272233
; RV32IM-NEXT: ret
19282234
;
19292235
; RV64IM-LABEL: select_redundant_czero_eqz2:
19302236
; RV64IM: # %bb.0: # %entry
1931-
; RV64IM-NEXT: bnez a0, .LBB50_2
2237+
; RV64IM-NEXT: bnez a0, .LBB58_2
19322238
; RV64IM-NEXT: # %bb.1: # %entry
19332239
; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data)
19342240
; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data)
1935-
; RV64IM-NEXT: .LBB50_2: # %entry
2241+
; RV64IM-NEXT: .LBB58_2: # %entry
19362242
; RV64IM-NEXT: sd a0, 0(a1)
19372243
; RV64IM-NEXT: ret
19382244
;

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