Simplify "Optimize away mask of 63 for shl ( zext (and i32 63)))"

This reverts commit 40e9092 and replace
it with a simple constant 63 mask

Author: badumbatish

llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp

@@ -70,11 +70,6 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel {
   bool SelectAddrOperands32(SDValue Op, SDValue &Offset, SDValue &Addr);
   bool SelectAddrOperands64(SDValue Op, SDValue &Offset, SDValue &Addr);
 
-  bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
-
-  bool selectShiftMask64FromI32(SDValue N, SDValue &ShAmt) {
-    return selectShiftMask(N, 64, ShAmt);
-  }
 // Include the pieces autogenerated from the target description.
 #include "WebAssemblyGenDAGISel.inc"
 
@@ -544,36 +539,6 @@ bool WebAssemblyDAGToDAGISel::SelectAddrOperands64(SDValue Op, SDValue &Offset,
   return SelectAddrOperands(MVT::i64, WebAssembly::CONST_I64, Op, Offset, Addr);
 }
 
-bool WebAssemblyDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
-                                              SDValue &ShAmt) {
-
-  ShAmt = N;
-
-  if (ShAmt.getOpcode() == ISD::AND &&
-      isa<ConstantSDNode>(ShAmt.getOperand(1))) {
-    const APInt &AndMask = ShAmt.getConstantOperandAPInt(1);
-
-    // Since the max shift amount is a power of 2 we can subtract 1 to make a
-    // mask that covers the bits needed to represent all shift amounts.
-    assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!");
-    APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1);
-
-    if (ShMask.isSubsetOf(AndMask)) {
-      ShAmt = ShAmt.getOperand(0);
-    } else {
-      // SimplifyDemandedBits may have optimized the mask so try restoring any
-      // bits that are known zero.
-      KnownBits Known = CurDAG->computeKnownBits(ShAmt.getOperand(0));
-      if (ShMask.isSubsetOf(AndMask | Known.Zero))
-        ShAmt = ShAmt.getOperand(0);
-    }
-    return true;
-  }
-
-  // TODO: Port rest of riscv if applicable
-  return false;
-}
-
 /// This pass converts a legalized DAG into a WebAssembly-specific DAG, ready
 /// for instruction scheduling.
 FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM,

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

@@ -3343,6 +3343,7 @@ static SDValue performAnyAllCombine(SDNode *N, SelectionDAG &DAG) {
       Ret = DAG.getNOT(DL, Ret, MVT::i1);
     return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
   };
+
   if (SDValue AnyTrueEQ = CombineSetCC(Intrinsic::wasm_anytrue, ISD::SETEQ,
                                        Intrinsic::wasm_alltrue))
     return AnyTrueEQ;

llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td

@@ -44,10 +44,6 @@ multiclass ComparisonInt<CondCode cond, string name, bits<32> i32Inst, bits<32>
                 !strconcat("i64.", name), i64Inst>;
 }
 
-// ComplexPattern
-def shiftMask64FromI32
-    : ComplexPattern<i32, 1, "selectShiftMask64FromI32", [], [], 0>;
-
 // The spaces after the names are for aesthetic purposes only, to make
 // operands line up vertically after tab expansion.
 let isCommutable = 1 in
@@ -105,15 +101,15 @@ def : Pat<(shl I64:$lhs, (and I64:$rhs, 63)), (SHL_I64 I64:$lhs, I64:$rhs)>;
 def : Pat<(sra I64:$lhs, (and I64:$rhs, 63)), (SHR_S_I64 I64:$lhs, I64:$rhs)>;
 def : Pat<(srl I64:$lhs, (and I64:$rhs, 63)), (SHR_U_I64 I64:$lhs, I64:$rhs)>;
 
-def : Pat<(shl I64:$lhs, (zext(shiftMask64FromI32 I32:$rhs))),
-          (SHL_I64 I64:$lhs, (I64_EXTEND_U_I32 I32:$rhs))>;
-
 // Optimize away an explicit mask on a rotate count.
 def : Pat<(rotl I32:$lhs, (and I32:$rhs, 31)), (ROTL_I32 I32:$lhs, I32:$rhs)>;
 def : Pat<(rotr I32:$lhs, (and I32:$rhs, 31)), (ROTR_I32 I32:$lhs, I32:$rhs)>;
 def : Pat<(rotl I64:$lhs, (and I64:$rhs, 63)), (ROTL_I64 I64:$lhs, I64:$rhs)>;
 def : Pat<(rotr I64:$lhs, (and I64:$rhs, 63)), (ROTR_I64 I64:$lhs, I64:$rhs)>;
 
+def : Pat<(shl I64:$lhs, (zext (and I32:$rhs, 63))),
+                               (SHL_I64 I64:$lhs, (I64_EXTEND_U_I32 I32:$rhs))>;
+
 defm SELECT_I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs, I32:$cond),
                     (outs), (ins),
                     [(set I32:$dst, (select I32:$cond, I32:$lhs, I32:$rhs))],