fixup! Address review comments

Author: virginia-cangelosi

llvm/lib/Target/AArch64/AArch64InstrFormats.td

@@ -5487,7 +5487,7 @@ multiclass IntegerToFP<bits<2> rmode, bits<3> opcode, string asm, SDPatternOpera
   }
 }
 
-multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator op, SDPatternOperator node = null_frag> {
+multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator node = null_frag> {
   // 32-bit to half-precision
   def HSr: BaseIntegerToFPUnscaled<rmode, opcode, FPR32, FPR16, f16, asm, node> {
     let Inst{31} = 0; // 32-bit FPR flag
@@ -5512,16 +5512,13 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
     let Inst{23-22} = 0b00; // 32-bit FPR flag
   }
 
-  def : Pat<(f16 (op (i32 FPR32:$Rn))),
-          (!cast<Instruction>(NAME # HSr) $Rn)>;
-
-  def : Pat<(f16 (op (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
+  def : Pat<(f16 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
           (!cast<Instruction>(NAME # HSr) (EXTRACT_SUBREG $Rn, ssub))>;
-  def : Pat<(f64 (op (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
+  def : Pat<(f64 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
           (!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG $Rn, ssub))>;
-  def : Pat<(f16 (op (i64 (extractelt (v2i64 V128:$Rn), (i64 0))))),
+  def : Pat<(f16 (node (i64 (extractelt (v2i64 V128:$Rn), (i64 0))))),
           (!cast<Instruction>(NAME # HDr) (EXTRACT_SUBREG $Rn, dsub))>;
-  def : Pat<(f32 (op (i64 (extractelt (v2i64 V128:$Rn), (i64 0))))),
+  def : Pat<(f32 (node (i64 (extractelt (v2i64 V128:$Rn), (i64 0))))),
           (!cast<Instruction>(NAME # SDr) (EXTRACT_SUBREG $Rn, dsub))>;
 }