Update llvm/test/CodeGen/RISCV/pr145363.ll

topperc · arsenm · web-flow · commit 8f66d8a82839 · 2025-06-26T23:28:06.000-07:00
Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;
diff --git a/llvm/test/CodeGen/RISCV/pr145363.ll b/llvm/test/CodeGen/RISCV/pr145363.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
 
-; These two loads will CSE, we need to conversatively combine the range
+; These two loads will CSE, we need to conservatively combine the range
 ; metadata. The final assembly should not contain an OR.
 define i32 @f(ptr %p) {
 ; CHECK-LABEL: f:
