@@ -89,15 +89,6 @@ class RISCVVLOptimizer : public MachineFunctionPass {
8989 bool isCandidate (const MachineInstr &MI) const ;
9090 void transfer (const MachineInstr &MI);
9191
92- // / Returns all uses of vector virtual registers.
93- auto vector_uses (const MachineInstr &MI) const {
94- auto Pred = [this ](const MachineOperand &MO) -> bool {
95- return MO.isReg () && MO.getReg ().isVirtual () &&
96- RISCVRegisterInfo::isRVVRegClass (MRI->getRegClass (MO.getReg ()));
97- };
98- return make_filter_range (MI.uses (), Pred);
99- }
100-
10192 // / For a given instruction, records what elements of it are demanded by
10293 // / downstream users.
10394 DenseMap<const MachineInstr *, DemandedVL> DemandedVLs;
@@ -1634,12 +1625,18 @@ static bool isPhysical(const MachineOperand &MO) {
16341625 return MO.isReg () && MO.getReg ().isPhysical ();
16351626}
16361627
1628+ static bool isVirtualVec (const MachineOperand &MO) {
1629+ return MO.isReg () && MO.getReg ().isVirtual () &&
1630+ RISCVRegisterInfo::isRVVRegClass (
1631+ MO.getParent ()->getMF ()->getRegInfo ().getRegClass (MO.getReg ()));
1632+ }
1633+
16371634// / Look through \p MI's operands and propagate what it demands to its uses.
16381635void RISCVVLOptimizer::transfer (const MachineInstr &MI) {
16391636 if (!isSupportedInstr (MI) || !checkUsers (MI) || any_of (MI.defs (), isPhysical))
16401637 DemandedVLs[&MI] = DemandedVL::vlmax ();
16411638
1642- for (const MachineOperand &MO : vector_uses (MI)) {
1639+ for (const MachineOperand &MO : make_filter_range (MI. uses (), isVirtualVec )) {
16431640 const MachineInstr *Def = MRI->getVRegDef (MO.getReg ());
16441641 DemandedVL Prev = DemandedVLs[Def];
16451642 DemandedVLs[Def] = max (DemandedVLs[Def], getMinimumVLForUser (MO));
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