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[AArch64] Remove SIMDLongThreeVectorTiedBHSabal tablegen class.
Similar to #152987 this removes SIMDLongThreeVectorTiedBHSabal as it is equivalent to SIMDLongThreeVectorTiedBHS with a better TriOpFrag pattern.
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‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 0 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -7405,50 +7405,6 @@ multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
74057405
(extract_high_v4i32 (v4i32 V128:$Rm))))]>;
74067406
}
74077407

7408-
multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
7409-
string asm,
7410-
SDPatternOperator OpNode> {
7411-
def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
7412-
V128, V64, V64,
7413-
asm, ".8h", ".8b", ".8b",
7414-
[(set (v8i16 V128:$dst),
7415-
(add (v8i16 V128:$Rd),
7416-
(zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
7417-
def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
7418-
V128, V128, V128,
7419-
asm#"2", ".8h", ".16b", ".16b",
7420-
[(set (v8i16 V128:$dst),
7421-
(add (v8i16 V128:$Rd),
7422-
(zext (v8i8 (OpNode (extract_high_v16i8 (v16i8 V128:$Rn)),
7423-
(extract_high_v16i8 (v16i8 V128:$Rm)))))))]>;
7424-
def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
7425-
V128, V64, V64,
7426-
asm, ".4s", ".4h", ".4h",
7427-
[(set (v4i32 V128:$dst),
7428-
(add (v4i32 V128:$Rd),
7429-
(zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
7430-
def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
7431-
V128, V128, V128,
7432-
asm#"2", ".4s", ".8h", ".8h",
7433-
[(set (v4i32 V128:$dst),
7434-
(add (v4i32 V128:$Rd),
7435-
(zext (v4i16 (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
7436-
(extract_high_v8i16 (v8i16 V128:$Rm)))))))]>;
7437-
def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
7438-
V128, V64, V64,
7439-
asm, ".2d", ".2s", ".2s",
7440-
[(set (v2i64 V128:$dst),
7441-
(add (v2i64 V128:$Rd),
7442-
(zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
7443-
def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
7444-
V128, V128, V128,
7445-
asm#"2", ".2d", ".4s", ".4s",
7446-
[(set (v2i64 V128:$dst),
7447-
(add (v2i64 V128:$Rd),
7448-
(zext (v2i32 (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7449-
(extract_high_v4i32 (v4i32 V128:$Rm)))))))]>;
7450-
}
7451-
74527408
let isCommutable = 1 in
74537409
multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
74547410
SDPatternOperator OpNode = null_frag> {

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -6782,44 +6782,45 @@ def : Pat <(f64 (uint_to_fp (i32
67826782
// Advanced SIMD three different-sized vector instructions.
67836783
//===----------------------------------------------------------------------===//
67846784

6785-
defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
6786-
defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
6787-
defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
6788-
defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
6785+
defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
6786+
defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
6787+
defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
6788+
defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
67896789
let isCommutable = 1 in
6790-
defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull", AArch64pmull>;
6791-
defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal", abds>;
6790+
defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull", AArch64pmull>;
6791+
defm SABAL : SIMDLongThreeVectorTiedBHS<0,0b0101,"sabal",
6792+
TriOpFrag<(add node:$LHS, (zext (abds node:$MHS, node:$RHS)))>>;
67926793
defm SABDL : SIMDLongThreeVectorBHS<0, 0b0111, "sabdl",
67936794
BinOpFrag<(zext (abds node:$LHS, node:$RHS))>>;
67946795
defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
6795-
BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
6796+
BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
67966797
defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
67976798
BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
67986799
defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
6799-
TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>>;
6800+
TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>>;
68006801
defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
6801-
TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>>;
6802+
TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>>;
68026803
defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", AArch64smull>;
68036804
defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal", saddsat>;
68046805
defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl", ssubsat>;
6805-
defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
6806-
int_aarch64_neon_sqdmull>;
6806+
defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull", int_aarch64_neon_sqdmull>;
68076807
let isCommutable = 0 in
68086808
defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
68096809
BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
68106810
defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
68116811
BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
6812-
defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal", abdu>;
6812+
defm UABAL : SIMDLongThreeVectorTiedBHS<1, 0b0101, "uabal",
6813+
TriOpFrag<(add node:$LHS, (zext (abdu node:$MHS, node:$RHS)))>>;
68136814
defm UABDL : SIMDLongThreeVectorBHS<1, 0b0111, "uabdl",
68146815
BinOpFrag<(zext (abdu node:$LHS, node:$RHS))>>;
68156816
defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
68166817
BinOpFrag<(add (zanyext node:$LHS), (zanyext node:$RHS))>>;
68176818
defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
68186819
BinOpFrag<(add node:$LHS, (zanyext node:$RHS))>>;
68196820
defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
6820-
TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>>;
6821+
TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>>;
68216822
defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
6822-
TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>>;
6823+
TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>>;
68236824
defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", AArch64umull>;
68246825
let isCommutable = 0 in
68256826
defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",

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