fixup! convert lambda to static func

Author: michaelmaitland

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -1014,48 +1014,48 @@ RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
   }
 }
 
-bool RISCVInstrInfo::trySimplifyCondBr(
-    MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
-    SmallVectorImpl<MachineOperand> &Cond) const {
+// Return true if MO definitely contains the value one.
+static bool isOne(MachineOperand &MO) {
+  if (MO.isImm() && MO.getImm() == 1)
+    return true;
 
-  if (!TBB || Cond.size() != 3)
+  if (!MO.isReg() || !MO.getReg().isVirtual())
     return false;
 
-  RISCVCC::CondCode CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
-  auto LHS = Cond[1];
-  auto RHS = Cond[2];
+  MachineRegisterInfo &MRI =
+      MO.getParent()->getParent()->getParent()->getRegInfo();
+  MachineInstr *DefMI = MRI.getUniqueVRegDef(MO.getReg());
+  if (!DefMI)
+    return false;
 
-  // Return true if MO definitely contains the value one.
-  auto isOne = [](MachineOperand &MO) -> bool {
-    if (MO.isImm() && MO.getImm() == 1)
-      return true;
+  // For now, just check the canonical one value.
+  if (DefMI->getOpcode() == RISCV::ADDI &&
+      DefMI->getOperand(1).getReg() == RISCV::X0 &&
+      DefMI->getOperand(2).getImm() == 1)
+    return true;
 
-    if (!MO.isReg() || !MO.getReg().isVirtual())
-      return false;
+  return false;
+}
 
-    MachineRegisterInfo &MRI =
-        MO.getParent()->getParent()->getParent()->getRegInfo();
-    MachineInstr *DefMI = MRI.getUniqueVRegDef(MO.getReg());
-    if (!DefMI)
-      return false;
+// Return true if MO definitely contains the value zero.
+static bool isZero(MachineOperand &MO) {
+  if (MO.isImm() && MO.getImm() == 0)
+    return true;
+  if (MO.isReg() && MO.getReg() == RISCV::X0)
+    return true;
+  return false;
+}
 
-    // For now, just check the canonical one value.
-    if (DefMI->getOpcode() == RISCV::ADDI &&
-        DefMI->getOperand(1).getReg() == RISCV::X0 &&
-        DefMI->getOperand(2).getImm() == 1)
-      return true;
+bool RISCVInstrInfo::trySimplifyCondBr(
+    MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+    SmallVectorImpl<MachineOperand> &Cond) const {
 
+  if (!TBB || Cond.size() != 3)
     return false;
-  };
 
-  // Return true if MO definitely contains the value zero.
-  auto isZero = [](MachineOperand &MO) -> bool {
-    if (MO.isImm() && MO.getImm() == 0)
-      return true;
-    if (MO.isReg() && MO.getReg() == RISCV::X0)
-      return true;
-    return false;
-  };
+  RISCVCC::CondCode CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
+  auto LHS = Cond[1];
+  auto RHS = Cond[2];
 
   MachineBasicBlock *Folded = nullptr;
   switch (CC) {