@@ -18791,22 +18791,15 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
1879118791 Function *F = CGM.getIntrinsic(Intrin, { Src0->getType() });
1879218792 return Builder.CreateCall(F, { Src0, Builder.getFalse() });
1879318793 }
18794- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
1879518794 case AMDGPU::BI__builtin_amdgcn_global_atomic_fmin_f64:
1879618795 case AMDGPU::BI__builtin_amdgcn_global_atomic_fmax_f64:
1879718796 case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f64:
1879818797 case AMDGPU::BI__builtin_amdgcn_flat_atomic_fmin_f64:
1879918798 case AMDGPU::BI__builtin_amdgcn_flat_atomic_fmax_f64:
18800- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f32:
18801- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16: {
18799+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f32: {
1880218800 Intrinsic::ID IID;
1880318801 llvm::Type *ArgTy = llvm::Type::getDoubleTy(getLLVMContext());
1880418802 switch (BuiltinID) {
18805- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
18806- ArgTy = llvm::FixedVectorType::get(
18807- llvm::Type::getHalfTy(getLLVMContext()), 2);
18808- IID = Intrinsic::amdgcn_global_atomic_fadd;
18809- break;
1881018803 case AMDGPU::BI__builtin_amdgcn_global_atomic_fmin_f64:
1881118804 IID = Intrinsic::amdgcn_global_atomic_fmin;
1881218805 break;
@@ -18826,11 +18819,6 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
1882618819 ArgTy = llvm::Type::getFloatTy(getLLVMContext());
1882718820 IID = Intrinsic::amdgcn_flat_atomic_fadd;
1882818821 break;
18829- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16:
18830- ArgTy = llvm::FixedVectorType::get(
18831- llvm::Type::getHalfTy(getLLVMContext()), 2);
18832- IID = Intrinsic::amdgcn_flat_atomic_fadd;
18833- break;
1883418822 }
1883518823 llvm::Value *Addr = EmitScalarExpr(E->getArg(0));
1883618824 llvm::Value *Val = EmitScalarExpr(E->getArg(1));
@@ -19231,7 +19219,9 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
1923119219 case AMDGPU::BI__builtin_amdgcn_ds_fminf:
1923219220 case AMDGPU::BI__builtin_amdgcn_ds_fmaxf:
1923319221 case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f32:
19234- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64: {
19222+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64:
19223+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
19224+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16: {
1923519225 llvm::AtomicRMWInst::BinOp BinOp;
1923619226 switch (BuiltinID) {
1923719227 case AMDGPU::BI__builtin_amdgcn_atomic_inc32:
@@ -19249,6 +19239,8 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
1924919239 case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_v2bf16:
1925019240 case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f32:
1925119241 case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64:
19242+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
19243+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16:
1925219244 BinOp = llvm::AtomicRMWInst::FAdd;
1925319245 break;
1925419246 case AMDGPU::BI__builtin_amdgcn_ds_fminf:
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