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[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)
This extension adds 8 load/store instructions with a scaled index addressing mode. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -189,6 +189,7 @@
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// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
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// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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// CHECK-EMPTY:
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// CHECK-NEXT: Supported Profiles
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// CHECK-NEXT: rva20s64

‎llvm/docs/RISCVUsage.rst‎

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@@ -429,6 +429,9 @@ The current vendor extensions supported are:
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``experimental-Xqcicsr``
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LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcisls``
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LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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Experimental C Intrinsics
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=========================
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‎llvm/docs/ReleaseNotes.md‎

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@@ -213,6 +213,8 @@ Changes to the RISC-V Backend
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between e.g. F and Zfinx code.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcicsr` (CSR)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcisls` (Scaled Load Store)
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extension.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -684,6 +684,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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"CORE-V Immediate Branching custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32,
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"Qualcomm uC CSR custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
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"Qualcomm uC Scaled Load Store custom opcode table");
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TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
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return MCDisassembler::Fail;

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1351,6 +1351,14 @@ def HasVendorXqcicsr
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AssemblerPredicate<(all_of FeatureVendorXqcicsr),
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"'Xqcicsr' (Qualcomm uC CSR Extension)">;
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def FeatureVendorXqcisls
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: RISCVExperimentalExtension<"xqcisls", 0, 2,
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"'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;
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def HasVendorXqcisls
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: Predicate<"Subtarget->hasVendorXqcisls()">,
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AssemblerPredicate<(all_of FeatureVendorXqcisls),
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"'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -22,6 +22,29 @@
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
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class QCILoad_ScaleIdx<bits<4> func4, string opcodestr>
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: RVInstRBase<0b111, OPC_CUSTOM_0,
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(outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
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opcodestr, "$rd, $rs1, $rs2, $shamt"> {
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bits<3> shamt;
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let Inst{31-28} = func4;
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let Inst{27-25} = shamt;
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}
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
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// rd corresponds to the source for the store 'rs3' described in the spec.
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class QCIStore_ScaleIdx<bits<4> func4, string opcodestr>
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: RVInstRBase<0b110, OPC_CUSTOM_1, (outs),
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(ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
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opcodestr, "$rd, $rs1, $rs2, $shamt"> {
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bits<3> shamt;
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let Inst{31-28} = func4;
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let Inst{27-25} = shamt;
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}
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
@@ -37,3 +60,15 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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"$rd, $rs1, $rs2">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr"
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let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in {
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def QC_LRB : QCILoad_ScaleIdx<0b1000, "qc.lrb">;
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def QC_LRH : QCILoad_ScaleIdx<0b1001, "qc.lrh">;
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def QC_LRW : QCILoad_ScaleIdx<0b1010, "qc.lrw">;
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def QC_LRBU : QCILoad_ScaleIdx<0b1011, "qc.lrbu">;
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def QC_LRHU : QCILoad_ScaleIdx<0b1100, "qc.lrhu">;
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def QC_SRB : QCIStore_ScaleIdx<0b1101, "qc.srb">;
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def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">;
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def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">;
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} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls"

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -741,6 +741,7 @@ Error RISCVISAInfo::checkDependency() {
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bool HasVector = Exts.count("zve32x") != 0;
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bool HasZvl = MinVLen != 0;
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bool HasZcmt = Exts.count("zcmt") != 0;
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static constexpr StringLiteral XqciExts[] = {{"xqcicsr"}, {"xqcisls"}};
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if (HasI && HasE)
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return getIncompatibleError("i", "e");
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return getIncompatibleError("xwchc", "zcb");
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}
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if (Exts.count("xqcicsr") != 0 && (XLen != 32)) {
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return getError("'xqcicsr' is only supported for 'rv32'");
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}
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for (auto Ext : XqciExts)
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if (Exts.count(Ext.str()) && (XLen != 32))
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return getError("'" + Twine(Ext) + "'" + " is only supported for 'rv32'");
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return Error::success();
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}

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -82,6 +82,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s
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; RUN: llc -mtriple=riscv32 -mattr=+xwchc %s -o - | FileCheck --check-prefix=RV32XWCHC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
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; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
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; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
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; RUN: llc -mtriple=riscv32 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s
@@ -387,6 +388,7 @@
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; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
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; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2"
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; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
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; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
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; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
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; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"
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; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"

‎llvm/test/MC/RISCV/xqcisls-invalid.s‎

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# Xqcisls - Qualcomm uC Scaled Load Store Extension
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisls < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
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# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisls < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
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# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
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qc.lrb x5, x2, x0, 4
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.lrb x5, x2, x4
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# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 7]
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qc.lrb x5, x2, x4, 12
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# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
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qc.lrb x5, 2, x4, 4
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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qc.lrb x5, x2, x4, 4
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# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
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qc.lrh x1, x12, x0, 2
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.lrh x1, x12, x6
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# CHECK-PLUS: :[[@LINE+1]]:21: error: immediate must be an integer in the range [0, 7]
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qc.lrh x1, x12, x6, 22
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# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
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qc.lrh x1, 12, x6, 2
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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qc.lrh x1, x12, x6, 2
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# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
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qc.lrw x15, x7, x0, 1
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.lrw x15, x7, x14
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# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
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qc.lrw x15, x7, x14, 11
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# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
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qc.lrw x15, 7, x14, 1
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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qc.lrw x15, x7, x14, 1
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# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
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qc.lrbu x9, x11, x0, 7
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.lrbu x9, x11, x4
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# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
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qc.lrbu x9, x11, x4, 37
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# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
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qc.lrbu x9, 11, x4, 7
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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qc.lrbu x9, x11, x4, 7
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# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
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qc.lrhu x16, x6, x0, 4
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.lrhu x16, x6, x10
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# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [0, 7]
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qc.lrhu x16, x6, x10, 44
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# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
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qc.lrhu x16, 6, x10, 4
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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qc.lrhu x16, x6, x10, 4
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# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
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qc.srb x0, x2, x0, 3
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.srb x0, x2, x8
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# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 7]
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qc.srb x0, x2, x8, 93
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# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
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qc.srb x0, 2, x8, 3
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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qc.srb x0, x2, x8, 3
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# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
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qc.srh x13, x0, x0, 6
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.srh x13, x0, x20
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# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 7]
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qc.srh x13, x0, x20, 76
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# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
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qc.srh x13, 0, x20, 6
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
116+
qc.srh x13, x0, x20, 6
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# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
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qc.srw x17, x18, x0, 0
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.srw x17, x18, x19
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# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [0, 7]
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qc.srw x17, x18, x19, 10
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# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
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qc.srw x17, 18, x19, 0
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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qc.srw x17, x18, x19, 0

‎llvm/test/MC/RISCV/xqcisls-valid.s‎

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# Xqcisls - Qualcomm uC Scaled Load Store Extension
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisls -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisls < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xqcisls -M no-aliases --no-print-imm-hex -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisls -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisls < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xqcisls --no-print-imm-hex -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# CHECK-INST: qc.lrb t0, sp, tp, 4
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# CHECK-ENC: encoding: [0x8b,0x72,0x41,0x88]
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qc.lrb x5, x2, x4, 4
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# CHECK-INST: qc.lrh ra, a2, t1, 2
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# CHECK-ENC: encoding: [0x8b,0x70,0x66,0x94]
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qc.lrh x1, x12, x6, 2
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# CHECK-INST: qc.lrw a5, t2, a4, 1
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# CHECK-ENC: encoding: [0x8b,0xf7,0xe3,0xa2]
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qc.lrw x15, x7, x14, 1
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# CHECK-INST: qc.lrbu s1, a1, tp, 7
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# CHECK-ENC: encoding: [0x8b,0xf4,0x45,0xbe]
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qc.lrbu x9, x11, x4, 7
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# CHECK-INST: qc.lrhu a6, t1, a0, 4
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# CHECK-ENC: encoding: [0x0b,0x78,0xa3,0xc8]
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qc.lrhu x16, x6, x10, 4
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# CHECK-INST: qc.srb zero, sp, s0, 3
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# CHECK-ENC: encoding: [0x2b,0x60,0x81,0xd6]
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qc.srb x0, x2, x8, 3
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# CHECK-INST: qc.srh a3, zero, s4, 6
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# CHECK-ENC: encoding: [0xab,0x66,0x40,0xed]
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qc.srh x13, x0, x20, 6
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# CHECK-INST: qc.srw a7, s2, s3, 0
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# CHECK-ENC: encoding: [0xab,0x68,0x39,0xf1]
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qc.srw x17, x18, x19, 0

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