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RKSimonRKSimon
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[X86] addConstantComments - add vector constant printing for (V)PMULLD instructions (#163949)
1 parent 38ce641 commit 8fd558d

36 files changed

+348
-347
lines changed

‎llvm/lib/Target/X86/X86MCInstLower.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1959,6 +1959,7 @@ static void addConstantComments(const MachineInstr *MI,
19591959
}
19601960

19611961
CASE_ARITH_RM(PMADDWD)
1962+
CASE_ARITH_RM(PMULLD)
19621963
CASE_ARITH_RM(PMULLW)
19631964
CASE_ARITH_RM(PMULHW)
19641965
CASE_ARITH_RM(PMULHUW)

‎llvm/test/CodeGen/X86/avx-shift.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ define <8 x i32> @vshift08_add(<8 x i32> %a, <8 x i32> %y) {
201201
define <4 x i32> @vshift13(<4 x i32> %in) {
202202
; CHECK-LABEL: vshift13:
203203
; CHECK: # %bb.0:
204-
; CHECK-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
204+
; CHECK-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,2,4,16]
205205
; CHECK-NEXT: retq
206206
%T = shl <4 x i32> %in, <i32 0, i32 1, i32 2, i32 4>
207207
ret <4 x i32> %T

‎llvm/test/CodeGen/X86/avx2-arith.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -199,12 +199,12 @@ define <8 x i32> @mul_const5(<8 x i32> %x) {
199199
define <8 x i32> @mul_const6(<8 x i32> %x) {
200200
; X86-LABEL: mul_const6:
201201
; X86: # %bb.0:
202-
; X86-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
202+
; X86-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # [0,0,0,2,0,2,0,0]
203203
; X86-NEXT: retl
204204
;
205205
; X64-LABEL: mul_const6:
206206
; X64: # %bb.0:
207-
; X64-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
207+
; X64-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [0,0,0,2,0,2,0,0]
208208
; X64-NEXT: retq
209209
%y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 2, i32 0, i32 2, i32 0, i32 0>
210210
ret <8 x i32> %y

‎llvm/test/CodeGen/X86/combine-mul.ll‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ define <4 x i32> @combine_vec_mul_pow2a(<4 x i32> %x) {
6666
define <4 x i32> @combine_vec_mul_pow2b(<4 x i32> %x) {
6767
; SSE-LABEL: combine_vec_mul_pow2b:
6868
; SSE: # %bb.0:
69-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
69+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1,2,4,16]
7070
; SSE-NEXT: retq
7171
;
7272
; AVX-LABEL: combine_vec_mul_pow2b:
@@ -120,12 +120,12 @@ define <4 x i32> @combine_vec_mul_negpow2a(<4 x i32> %x) {
120120
define <4 x i32> @combine_vec_mul_negpow2b(<4 x i32> %x) {
121121
; SSE-LABEL: combine_vec_mul_negpow2b:
122122
; SSE: # %bb.0:
123-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
123+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4294967295,4294967294,4294967292,4294967280]
124124
; SSE-NEXT: retq
125125
;
126126
; AVX-LABEL: combine_vec_mul_negpow2b:
127127
; AVX: # %bb.0:
128-
; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
128+
; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4294967295,4294967294,4294967292,4294967280]
129129
; AVX-NEXT: retq
130130
%1 = mul <4 x i32> %x, <i32 -1, i32 -2, i32 -4, i32 -16>
131131
ret <4 x i32> %1
@@ -176,12 +176,12 @@ define <4 x i64> @combine_vec_mul_negpow2c(<4 x i64> %x) {
176176
define <4 x i32> @combine_vec_mul_shl_const(<4 x i32> %x) {
177177
; SSE-LABEL: combine_vec_mul_shl_const:
178178
; SSE: # %bb.0:
179-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
179+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,12,1280,458752]
180180
; SSE-NEXT: retq
181181
;
182182
; AVX-LABEL: combine_vec_mul_shl_const:
183183
; AVX: # %bb.0:
184-
; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
184+
; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [2,12,1280,458752]
185185
; AVX-NEXT: retq
186186
%1 = shl <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>
187187
%2 = mul <4 x i32> %1, <i32 1, i32 3, i32 5, i32 7>
@@ -193,7 +193,7 @@ define <4 x i32> @combine_vec_mul_shl_oneuse0(<4 x i32> %x, <4 x i32> %y) {
193193
; SSE-LABEL: combine_vec_mul_shl_oneuse0:
194194
; SSE: # %bb.0:
195195
; SSE-NEXT: pmulld %xmm1, %xmm0
196-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
196+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,256,65536]
197197
; SSE-NEXT: retq
198198
;
199199
; AVX-LABEL: combine_vec_mul_shl_oneuse0:
@@ -210,7 +210,7 @@ define <4 x i32> @combine_vec_mul_shl_oneuse1(<4 x i32> %x, <4 x i32> %y) {
210210
; SSE-LABEL: combine_vec_mul_shl_oneuse1:
211211
; SSE: # %bb.0:
212212
; SSE-NEXT: pmulld %xmm1, %xmm0
213-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
213+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,256,65536]
214214
; SSE-NEXT: retq
215215
;
216216
; AVX-LABEL: combine_vec_mul_shl_oneuse1:
@@ -226,7 +226,7 @@ define <4 x i32> @combine_vec_mul_shl_oneuse1(<4 x i32> %x, <4 x i32> %y) {
226226
define <4 x i32> @combine_vec_mul_shl_multiuse0(<4 x i32> %x, <4 x i32> %y) {
227227
; SSE-LABEL: combine_vec_mul_shl_multiuse0:
228228
; SSE: # %bb.0:
229-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
229+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,256,65536]
230230
; SSE-NEXT: pmulld %xmm0, %xmm1
231231
; SSE-NEXT: paddd %xmm1, %xmm0
232232
; SSE-NEXT: retq
@@ -246,7 +246,7 @@ define <4 x i32> @combine_vec_mul_shl_multiuse0(<4 x i32> %x, <4 x i32> %y) {
246246
define <4 x i32> @combine_vec_mul_shl_multiuse1(<4 x i32> %x, <4 x i32> %y) {
247247
; SSE-LABEL: combine_vec_mul_shl_multiuse1:
248248
; SSE: # %bb.0:
249-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
249+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,256,65536]
250250
; SSE-NEXT: pmulld %xmm0, %xmm1
251251
; SSE-NEXT: paddd %xmm1, %xmm0
252252
; SSE-NEXT: retq
@@ -268,13 +268,13 @@ define <4 x i32> @combine_vec_mul_shl_multiuse1(<4 x i32> %x, <4 x i32> %y) {
268268
define <4 x i32> @combine_vec_mul_add(<4 x i32> %x) {
269269
; SSE-LABEL: combine_vec_mul_add:
270270
; SSE: # %bb.0:
271-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
271+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4,6,2,0]
272272
; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
273273
; SSE-NEXT: retq
274274
;
275275
; AVX-LABEL: combine_vec_mul_add:
276276
; AVX: # %bb.0:
277-
; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
277+
; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4,6,2,0]
278278
; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
279279
; AVX-NEXT: retq
280280
%1 = add <4 x i32> %x, <i32 1, i32 2, i32 8, i32 16>

‎llvm/test/CodeGen/X86/combine-shl.ll‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ define <4 x i32> @combine_vec_shl_known_zero1(<4 x i32> %x) {
9797
; SSE41-LABEL: combine_vec_shl_known_zero1:
9898
; SSE41: # %bb.0:
9999
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
100-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
100+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [65536,32768,16384,8192]
101101
; SSE41-NEXT: retq
102102
;
103103
; AVX-LABEL: combine_vec_shl_known_zero1:
@@ -207,7 +207,7 @@ define <4 x i32> @combine_vec_shl_shl1(<4 x i32> %x) {
207207
;
208208
; SSE41-LABEL: combine_vec_shl_shl1:
209209
; SSE41: # %bb.0:
210-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
210+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [16,64,256,1024]
211211
; SSE41-NEXT: retq
212212
;
213213
; AVX-LABEL: combine_vec_shl_shl1:
@@ -323,10 +323,10 @@ define <8 x i32> @combine_vec_shl_ext_shl2(<8 x i16> %x) {
323323
; SSE41-LABEL: combine_vec_shl_ext_shl2:
324324
; SSE41: # %bb.0:
325325
; SSE41-NEXT: pmovsxwd %xmm0, %xmm2
326-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
326+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [131072,524288,2097152,8388608]
327327
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
328328
; SSE41-NEXT: pmovsxwd %xmm0, %xmm1
329-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
329+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [33554432,134217728,536870912,2147483648]
330330
; SSE41-NEXT: movdqa %xmm2, %xmm0
331331
; SSE41-NEXT: retq
332332
;
@@ -683,7 +683,7 @@ define <4 x i32> @combine_vec_shl_add1(<4 x i32> %x) {
683683
;
684684
; SSE41-LABEL: combine_vec_shl_add1:
685685
; SSE41: # %bb.0:
686-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
686+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,8,16]
687687
; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
688688
; SSE41-NEXT: retq
689689
;
@@ -736,7 +736,7 @@ define <4 x i32> @combine_vec_shl_or1(<4 x i32> %x) {
736736
;
737737
; SSE41-LABEL: combine_vec_shl_or1:
738738
; SSE41: # %bb.0:
739-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
739+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,4,8,16]
740740
; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
741741
; SSE41-NEXT: retq
742742
;
@@ -765,7 +765,7 @@ define <4 x i32> @combine_vec_shl_mul0(<4 x i32> %x) {
765765
;
766766
; SSE41-LABEL: combine_vec_shl_mul0:
767767
; SSE41: # %bb.0:
768-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
768+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [20,20,20,20]
769769
; SSE41-NEXT: retq
770770
;
771771
; AVX2-LABEL: combine_vec_shl_mul0:
@@ -796,12 +796,12 @@ define <4 x i32> @combine_vec_shl_mul1(<4 x i32> %x) {
796796
;
797797
; SSE41-LABEL: combine_vec_shl_mul1:
798798
; SSE41: # %bb.0:
799-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
799+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [10,24,56,128]
800800
; SSE41-NEXT: retq
801801
;
802802
; AVX-LABEL: combine_vec_shl_mul1:
803803
; AVX: # %bb.0:
804-
; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
804+
; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [10,24,56,128]
805805
; AVX-NEXT: retq
806806
%1 = mul <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
807807
%2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>
@@ -823,7 +823,7 @@ define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) {
823823
;
824824
; SSE41-LABEL: combine_vec_add_shl_nonsplat:
825825
; SSE41: # %bb.0:
826-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
826+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4,8,16,32]
827827
; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
828828
; SSE41-NEXT: retq
829829
;
@@ -863,7 +863,7 @@ define <4 x i32> @combine_vec_add_shl_and_nonsplat(<4 x i32> %a0) {
863863
; SSE41: # %bb.0:
864864
; SSE41-NEXT: pxor %xmm1, %xmm1
865865
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7]
866-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
866+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [4,8,16,32]
867867
; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
868868
; SSE41-NEXT: retq
869869
;

‎llvm/test/CodeGen/X86/combine-srem.ll‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -272,7 +272,7 @@ define <4 x i32> @combine_vec_srem_by_pow2b(<4 x i32> %x) {
272272
; SSE-NEXT: psrad $2, %xmm2
273273
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
274274
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1],xmm2[2,3,4,5,6,7]
275-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
275+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [1,2,4,8]
276276
; SSE-NEXT: psubd %xmm2, %xmm0
277277
; SSE-NEXT: retq
278278
;
@@ -291,7 +291,7 @@ define <4 x i32> @combine_vec_srem_by_pow2b(<4 x i32> %x) {
291291
; AVX1-NEXT: vpsrad $2, %xmm1, %xmm1
292292
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
293293
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
294-
; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
294+
; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,2,4,8]
295295
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
296296
; AVX1-NEXT: retq
297297
;
@@ -336,7 +336,7 @@ define <4 x i32> @combine_vec_srem_by_pow2b_neg(<4 x i32> %x) {
336336
; SSE-NEXT: psrld $1, %xmm1
337337
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
338338
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
339-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
339+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [4294967294,4294967292,4294967288,4294967280]
340340
; SSE-NEXT: paddd %xmm1, %xmm0
341341
; SSE-NEXT: retq
342342
;
@@ -358,7 +358,7 @@ define <4 x i32> @combine_vec_srem_by_pow2b_neg(<4 x i32> %x) {
358358
; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
359359
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
360360
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
361-
; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
361+
; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [4294967294,4294967292,4294967288,4294967280]
362362
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
363363
; AVX1-NEXT: retq
364364
;
@@ -368,7 +368,7 @@ define <4 x i32> @combine_vec_srem_by_pow2b_neg(<4 x i32> %x) {
368368
; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
369369
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
370370
; AVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
371-
; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
371+
; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [4294967294,4294967292,4294967288,4294967280]
372372
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
373373
; AVX2-NEXT: retq
374374
%1 = srem <4 x i32> %x, <i32 -2, i32 -4, i32 -8, i32 -16>

‎llvm/test/CodeGen/X86/combine-urem.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -327,7 +327,7 @@ define <4 x i32> @combine_vec_urem_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
327327
; SSE-NEXT: pslld $23, %xmm1
328328
; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
329329
; SSE-NEXT: cvttps2dq %xmm1, %xmm1
330-
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
330+
; SSE-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1,4,8,16]
331331
; SSE-NEXT: pcmpeqd %xmm2, %xmm2
332332
; SSE-NEXT: paddd %xmm1, %xmm2
333333
; SSE-NEXT: pand %xmm2, %xmm0
@@ -338,7 +338,7 @@ define <4 x i32> @combine_vec_urem_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
338338
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
339339
; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
340340
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
341-
; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
341+
; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,4,8,16]
342342
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
343343
; AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
344344
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0

‎llvm/test/CodeGen/X86/madd.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2072,14 +2072,14 @@ define <4 x i32> @pmaddwd_negative2(<8 x i16> %A) {
20722072
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
20732073
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
20742074
; AVX1-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,7,42,32]
2075-
; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
2075+
; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [32768,4294934528,0,0]
20762076
; AVX1-NEXT: vphaddd %xmm0, %xmm1, %xmm0
20772077
; AVX1-NEXT: retq
20782078
;
20792079
; AVX256-LABEL: pmaddwd_negative2:
20802080
; AVX256: # %bb.0:
20812081
; AVX256-NEXT: vpmovsxwd %xmm0, %ymm0
2082-
; AVX256-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
2082+
; AVX256-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [32768,4294934528,0,0,1,7,42,32]
20832083
; AVX256-NEXT: vextracti128 $1, %ymm0, %xmm1
20842084
; AVX256-NEXT: vphaddd %xmm1, %xmm0, %xmm0
20852085
; AVX256-NEXT: vzeroupper

‎llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ define <4 x i1> @p4_vector_urem_by_const__splat(<4 x i32> %x, <4 x i32> %y) {
100100
; SSE4-LABEL: p4_vector_urem_by_const__splat:
101101
; SSE4: # %bb.0:
102102
; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
103-
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
103+
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2863311531,2863311531,2863311531,2863311531]
104104
; SSE4-NEXT: psrld $1, %xmm0
105105
; SSE4-NEXT: movdqa {{.*#+}} xmm1 = [715827883,715827883,715827883,715827883]
106106
; SSE4-NEXT: pcmpgtd %xmm0, %xmm1
@@ -145,7 +145,7 @@ define <4 x i1> @p5_vector_urem_by_const__nonsplat(<4 x i32> %x, <4 x i32> %y) {
145145
; SSE4-LABEL: p5_vector_urem_by_const__nonsplat:
146146
; SSE4: # %bb.0:
147147
; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
148-
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
148+
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2863311531,3435973837,2863311531,954437177]
149149
; SSE4-NEXT: pmovzxdq {{.*#+}} xmm1 = [1,2147483648]
150150
; SSE4-NEXT: pmuludq %xmm0, %xmm1
151151
; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
@@ -159,7 +159,7 @@ define <4 x i1> @p5_vector_urem_by_const__nonsplat(<4 x i32> %x, <4 x i32> %y) {
159159
; AVX2-LABEL: p5_vector_urem_by_const__nonsplat:
160160
; AVX2: # %bb.0:
161161
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
162-
; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
162+
; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [2863311531,3435973837,2863311531,954437177]
163163
; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
164164
; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
165165
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
@@ -196,7 +196,7 @@ define <4 x i1> @p6_vector_urem_by_const__nonsplat_undef0(<4 x i32> %x, <4 x i32
196196
; SSE4-LABEL: p6_vector_urem_by_const__nonsplat_undef0:
197197
; SSE4: # %bb.0:
198198
; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
199-
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
199+
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2863311531,2863311531,2863311531,2863311531]
200200
; SSE4-NEXT: movdqa %xmm0, %xmm1
201201
; SSE4-NEXT: psrld $1, %xmm1
202202
; SSE4-NEXT: pslld $31, %xmm0
@@ -312,7 +312,7 @@ define <4 x i1> @p8_vector_urem_by_const__nonsplat_undef3(<4 x i32> %x, <4 x i32
312312
; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
313313
; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
314314
; SSE4-NEXT: psrld $2, %xmm2
315-
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
315+
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [6,6,6,6]
316316
; SSE4-NEXT: psubd %xmm2, %xmm0
317317
; SSE4-NEXT: pxor %xmm1, %xmm1
318318
; SSE4-NEXT: pcmpeqd %xmm1, %xmm0

‎llvm/test/CodeGen/X86/pmul.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ define <4 x i32> @mul_v4i32c(<4 x i32> %i) nounwind {
9191
;
9292
; SSE41-LABEL: mul_v4i32c:
9393
; SSE41: # %bb.0: # %entry
94-
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
94+
; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [117,117,117,117]
9595
; SSE41-NEXT: retq
9696
;
9797
; AVX-LABEL: mul_v4i32c:

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