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wangpc-ppwangpc-pp
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Use getRVVMCOpcode
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-68
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4 files changed

+71
-68
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 49 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -3679,52 +3679,6 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
36793679
return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
36803680
}
36813681

3682-
bool RISCVInstrInfo::isHighLatencyDef(int Opc) const {
3683-
switch (Opc) {
3684-
default:
3685-
return false;
3686-
// Integer div/rem.
3687-
case RISCV::DIV:
3688-
case RISCV::DIVW:
3689-
case RISCV::DIVU:
3690-
case RISCV::DIVUW:
3691-
case RISCV::REM:
3692-
case RISCV::REMW:
3693-
case RISCV::REMU:
3694-
case RISCV::REMUW:
3695-
// Floating-point div/rem/sqrt.
3696-
case RISCV::FDIV_H:
3697-
case RISCV::FDIV_S:
3698-
case RISCV::FDIV_D:
3699-
case RISCV::FDIV_H_INX:
3700-
case RISCV::FDIV_S_INX:
3701-
case RISCV::FDIV_D_INX:
3702-
case RISCV::FDIV_D_IN32X:
3703-
case RISCV::FSQRT_H:
3704-
case RISCV::FSQRT_S:
3705-
case RISCV::FSQRT_D:
3706-
case RISCV::FSQRT_H_INX:
3707-
case RISCV::FSQRT_S_INX:
3708-
case RISCV::FSQRT_D_INX:
3709-
case RISCV::FSQRT_D_IN32X:
3710-
// Integer div/rem.
3711-
case CASE_VFMA_OPCODE_VV(DIV):
3712-
case CASE_VFMA_OPCODE_VV(DIVU):
3713-
case CASE_VFMA_OPCODE_VV(REM):
3714-
case CASE_VFMA_OPCODE_VV(REMU):
3715-
// case CASE_VFMA_OPCODE_VX(DIV):
3716-
// case CASE_VFMA_OPCODE_VX(DIVU):
3717-
// case CASE_VFMA_OPCODE_VX(REM):
3718-
// case CASE_VFMA_OPCODE_VX(REMU):
3719-
// Vector floating-point div/sqrt.
3720-
case CASE_VFMA_OPCODE_VV(FDIV):
3721-
// case CASE_VFMA_OPCODE_VF(FRDIV):
3722-
// case CASE_VFMA_OPCODE_VV(FSQRT):
3723-
// case CASE_VFMA_OPCODE_VV(FRSQRT7):
3724-
return true;
3725-
}
3726-
}
3727-
37283682
#undef CASE_RVV_OPCODE_UNMASK_LMUL
37293683
#undef CASE_RVV_OPCODE_MASK_LMUL
37303684
#undef CASE_RVV_OPCODE_LMUL
@@ -4382,3 +4336,52 @@ RISCVInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
43824336

43834337
return std::make_unique<RISCVPipelinerLoopInfo>(LHS, RHS, Cond);
43844338
}
4339+
4340+
bool RISCVInstrInfo::isHighLatencyDef(int Opc) const {
4341+
unsigned RVVMCOpcode = RISCV::getRVVMCOpcode(Opc);
4342+
Opc = RVVMCOpcode ? RVVMCOpcode : Opc;
4343+
switch (Opc) {
4344+
default:
4345+
return false;
4346+
// Integer div/rem.
4347+
case RISCV::DIV:
4348+
case RISCV::DIVW:
4349+
case RISCV::DIVU:
4350+
case RISCV::DIVUW:
4351+
case RISCV::REM:
4352+
case RISCV::REMW:
4353+
case RISCV::REMU:
4354+
case RISCV::REMUW:
4355+
// Floating-point div/sqrt.
4356+
case RISCV::FDIV_H:
4357+
case RISCV::FDIV_S:
4358+
case RISCV::FDIV_D:
4359+
case RISCV::FDIV_H_INX:
4360+
case RISCV::FDIV_S_INX:
4361+
case RISCV::FDIV_D_INX:
4362+
case RISCV::FDIV_D_IN32X:
4363+
case RISCV::FSQRT_H:
4364+
case RISCV::FSQRT_S:
4365+
case RISCV::FSQRT_D:
4366+
case RISCV::FSQRT_H_INX:
4367+
case RISCV::FSQRT_S_INX:
4368+
case RISCV::FSQRT_D_INX:
4369+
case RISCV::FSQRT_D_IN32X:
4370+
// Vector integer div/rem
4371+
case RISCV::VDIV_VV:
4372+
case RISCV::VDIV_VX:
4373+
case RISCV::VDIVU_VV:
4374+
case RISCV::VDIVU_VX:
4375+
case RISCV::VREM_VV:
4376+
case RISCV::VREM_VX:
4377+
case RISCV::VREMU_VV:
4378+
case RISCV::VREMU_VX:
4379+
// Vector floating-point div/sqrt.
4380+
case RISCV::VFDIV_VV:
4381+
case RISCV::VFDIV_VF:
4382+
case RISCV::VFRDIV_VF:
4383+
case RISCV::VFSQRT_V:
4384+
case RISCV::VFRSQRT7_V:
4385+
return true;
4386+
}
4387+
}

‎llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1564,8 +1564,8 @@ define void @sink_splat_fdiv_scalable(ptr nocapture %a, float %x) {
15641564
; CHECK-NEXT: .LBB27_3: # %vector.body
15651565
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
15661566
; CHECK-NEXT: vl1re32.v v8, (a5)
1567-
; CHECK-NEXT: sub a6, a6, a3
15681567
; CHECK-NEXT: vfdiv.vf v8, v8, fa0
1568+
; CHECK-NEXT: sub a6, a6, a3
15691569
; CHECK-NEXT: vs1r.v v8, (a5)
15701570
; CHECK-NEXT: add a5, a5, a1
15711571
; CHECK-NEXT: bnez a6, .LBB27_3
@@ -1654,8 +1654,8 @@ define void @sink_splat_frdiv_scalable(ptr nocapture %a, float %x) {
16541654
; CHECK-NEXT: .LBB28_3: # %vector.body
16551655
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
16561656
; CHECK-NEXT: vl1re32.v v8, (a5)
1657-
; CHECK-NEXT: sub a6, a6, a3
16581657
; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
1658+
; CHECK-NEXT: sub a6, a6, a3
16591659
; CHECK-NEXT: vs1r.v v8, (a5)
16601660
; CHECK-NEXT: add a5, a5, a1
16611661
; CHECK-NEXT: bnez a6, .LBB28_3
@@ -2504,8 +2504,8 @@ define void @sink_splat_udiv_scalable(ptr nocapture %a, i32 signext %x) {
25042504
; CHECK-NEXT: .LBB42_3: # %vector.body
25052505
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
25062506
; CHECK-NEXT: vl2re32.v v8, (a6)
2507-
; CHECK-NEXT: sub a7, a7, a3
25082507
; CHECK-NEXT: vdivu.vx v8, v8, a1
2508+
; CHECK-NEXT: sub a7, a7, a3
25092509
; CHECK-NEXT: vs2r.v v8, (a6)
25102510
; CHECK-NEXT: add a6, a6, a5
25112511
; CHECK-NEXT: bnez a7, .LBB42_3
@@ -2595,8 +2595,8 @@ define void @sink_splat_sdiv_scalable(ptr nocapture %a, i32 signext %x) {
25952595
; CHECK-NEXT: .LBB43_3: # %vector.body
25962596
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
25972597
; CHECK-NEXT: vl2re32.v v8, (a6)
2598-
; CHECK-NEXT: sub a7, a7, a3
25992598
; CHECK-NEXT: vdiv.vx v8, v8, a1
2599+
; CHECK-NEXT: sub a7, a7, a3
26002600
; CHECK-NEXT: vs2r.v v8, (a6)
26012601
; CHECK-NEXT: add a6, a6, a5
26022602
; CHECK-NEXT: bnez a7, .LBB43_3
@@ -2686,8 +2686,8 @@ define void @sink_splat_urem_scalable(ptr nocapture %a, i32 signext %x) {
26862686
; CHECK-NEXT: .LBB44_3: # %vector.body
26872687
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
26882688
; CHECK-NEXT: vl2re32.v v8, (a6)
2689-
; CHECK-NEXT: sub a7, a7, a3
26902689
; CHECK-NEXT: vremu.vx v8, v8, a1
2690+
; CHECK-NEXT: sub a7, a7, a3
26912691
; CHECK-NEXT: vs2r.v v8, (a6)
26922692
; CHECK-NEXT: add a6, a6, a5
26932693
; CHECK-NEXT: bnez a7, .LBB44_3
@@ -2777,8 +2777,8 @@ define void @sink_splat_srem_scalable(ptr nocapture %a, i32 signext %x) {
27772777
; CHECK-NEXT: .LBB45_3: # %vector.body
27782778
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
27792779
; CHECK-NEXT: vl2re32.v v8, (a6)
2780-
; CHECK-NEXT: sub a7, a7, a3
27812780
; CHECK-NEXT: vrem.vx v8, v8, a1
2781+
; CHECK-NEXT: sub a7, a7, a3
27822782
; CHECK-NEXT: vs2r.v v8, (a6)
27832783
; CHECK-NEXT: add a6, a6, a5
27842784
; CHECK-NEXT: bnez a7, .LBB45_3

‎llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -92,15 +92,15 @@ define <vscale x 32 x bfloat> @vfsqrt_nxv32bf16(<vscale x 32 x bfloat> %v) stric
9292
; CHECK: # %bb.0:
9393
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
9494
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
95-
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
9695
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
9796
; CHECK-NEXT: vfsqrt.v v16, v16
9897
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
99-
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
98+
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
10099
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
101-
; CHECK-NEXT: vfsqrt.v v16, v24
100+
; CHECK-NEXT: vfsqrt.v v24, v24
102101
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
103-
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16
102+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
103+
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24
104104
; CHECK-NEXT: ret
105105
%r = call <vscale x 32 x bfloat> @llvm.experimental.constrained.sqrt.nxv32bf16(<vscale x 32 x bfloat> %v, metadata !"round.dynamic", metadata !"fpexcept.strict")
106106
ret <vscale x 32 x bfloat> %r
@@ -229,15 +229,15 @@ define <vscale x 32 x half> @vfsqrt_nxv32f16(<vscale x 32 x half> %v) strictfp {
229229
; ZVFHMIN: # %bb.0:
230230
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
231231
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
232-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
233232
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
234233
; ZVFHMIN-NEXT: vfsqrt.v v16, v16
235234
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
236-
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
235+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
237236
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
238-
; ZVFHMIN-NEXT: vfsqrt.v v16, v24
237+
; ZVFHMIN-NEXT: vfsqrt.v v24, v24
239238
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
240-
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
239+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
240+
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
241241
; ZVFHMIN-NEXT: ret
242242
%r = call <vscale x 32 x half> @llvm.experimental.constrained.sqrt.nxv32f16(<vscale x 32 x half> %v, metadata !"round.dynamic", metadata !"fpexcept.strict")
243243
ret <vscale x 32 x half> %r

‎llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -87,15 +87,15 @@ define <vscale x 32 x bfloat> @vfsqrt_nxv32bf16(<vscale x 32 x bfloat> %v) {
8787
; CHECK: # %bb.0:
8888
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
8989
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
90-
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
9190
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
9291
; CHECK-NEXT: vfsqrt.v v16, v16
9392
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
94-
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
93+
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
9594
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
96-
; CHECK-NEXT: vfsqrt.v v16, v24
95+
; CHECK-NEXT: vfsqrt.v v24, v24
9796
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
98-
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16
97+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
98+
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24
9999
; CHECK-NEXT: ret
100100
%r = call <vscale x 32 x bfloat> @llvm.sqrt.nxv32bf16(<vscale x 32 x bfloat> %v)
101101
ret <vscale x 32 x bfloat> %r
@@ -224,15 +224,15 @@ define <vscale x 32 x half> @vfsqrt_nxv32f16(<vscale x 32 x half> %v) {
224224
; ZVFHMIN: # %bb.0:
225225
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
226226
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
227-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
228227
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
229228
; ZVFHMIN-NEXT: vfsqrt.v v16, v16
230229
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
231-
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
230+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
232231
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
233-
; ZVFHMIN-NEXT: vfsqrt.v v16, v24
232+
; ZVFHMIN-NEXT: vfsqrt.v v24, v24
234233
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
235-
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
234+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
235+
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
236236
; ZVFHMIN-NEXT: ret
237237
%r = call <vscale x 32 x half> @llvm.sqrt.nxv32f16(<vscale x 32 x half> %v)
238238
ret <vscale x 32 x half> %r

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