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koachankoachan
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[𝘀𝗽𝗿] changes to main this commit is based on
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12 files changed

+830
-16
lines changed

12 files changed

+830
-16
lines changed

‎llvm/lib/Target/Sparc/SparcISelLowering.cpp‎

Lines changed: 26 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1704,8 +1704,10 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
17041704
setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
17051705
setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
17061706

1707-
setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1708-
setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1707+
setOperationAction(ISD::BITCAST, MVT::f32,
1708+
Subtarget->isVIS3() ? Legal : Expand);
1709+
setOperationAction(ISD::BITCAST, MVT::i32,
1710+
Subtarget->isVIS3() ? Legal : Expand);
17091711

17101712
// Sparc has no select or setcc: expand to SELECT_CC.
17111713
setOperationAction(ISD::SELECT, MVT::i32, Expand);
@@ -1737,9 +1739,16 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
17371739
setOperationAction(ISD::SUBC, MVT::i32, Legal);
17381740
setOperationAction(ISD::SUBE, MVT::i32, Legal);
17391741

1742+
if (Subtarget->isVIS3()) {
1743+
setOperationAction(ISD::ADDC, MVT::i64, Legal);
1744+
setOperationAction(ISD::ADDE, MVT::i64, Legal);
1745+
}
1746+
17401747
if (Subtarget->is64Bit()) {
1741-
setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1742-
setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1748+
setOperationAction(ISD::BITCAST, MVT::f64,
1749+
Subtarget->isVIS3() ? Legal : Expand);
1750+
setOperationAction(ISD::BITCAST, MVT::i64,
1751+
Subtarget->isVIS3() ? Legal : Expand);
17431752
setOperationAction(ISD::SELECT, MVT::i64, Expand);
17441753
setOperationAction(ISD::SETCC, MVT::i64, Expand);
17451754
setOperationAction(ISD::BR_CC, MVT::i64, Custom);
@@ -1748,7 +1757,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
17481757
setOperationAction(ISD::CTPOP, MVT::i64,
17491758
Subtarget->usePopc() ? Legal : Expand);
17501759
setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1751-
setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1760+
setOperationAction(ISD::CTLZ, MVT::i64,
1761+
Subtarget->isVIS3() ? Legal : Expand);
17521762
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
17531763
setOperationAction(ISD::ROTL , MVT::i64, Expand);
17541764
setOperationAction(ISD::ROTR , MVT::i64, Expand);
@@ -1810,7 +1820,7 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
18101820
setOperationAction(ISD::FREM , MVT::f32, Expand);
18111821
setOperationAction(ISD::FMA , MVT::f32, Expand);
18121822
setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1813-
setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1823+
setOperationAction(ISD::CTLZ, MVT::i32, Subtarget->isVIS3() ? Legal : Expand);
18141824
setOperationAction(ISD::ROTL , MVT::i32, Expand);
18151825
setOperationAction(ISD::ROTR , MVT::i32, Expand);
18161826
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
@@ -1849,8 +1859,10 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
18491859
if (Subtarget->is64Bit()) {
18501860
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
18511861
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1852-
setOperationAction(ISD::MULHU, MVT::i64, Expand);
1853-
setOperationAction(ISD::MULHS, MVT::i64, Expand);
1862+
setOperationAction(ISD::MULHU, MVT::i64,
1863+
Subtarget->isVIS3() ? Legal : Expand);
1864+
setOperationAction(ISD::MULHS, MVT::i64,
1865+
Subtarget->isVIS3() ? Legal : Expand);
18541866

18551867
setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
18561868
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
@@ -3560,6 +3572,12 @@ bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const {
35603572
return true;
35613573
}
35623574

3575+
bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
3576+
bool ForCodeSize) const {
3577+
return Subtarget->isVIS() && (VT == MVT::f32 || VT == MVT::f64) &&
3578+
Imm.isZero();
3579+
}
3580+
35633581
// Override to disable global variable loading on Linux.
35643582
void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
35653583
if (!Subtarget->isTargetLinux())

‎llvm/lib/Target/Sparc/SparcISelLowering.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,9 @@ namespace llvm {
207207
return VT != MVT::f128;
208208
}
209209

210+
bool isFPImmLegal(const APFloat &Imm, EVT VT,
211+
bool ForCodeSize) const override;
212+
210213
bool shouldInsertFencesForAtomic(const Instruction *I) const override {
211214
// FIXME: We insert fences for each atomics and generate
212215
// sub-optimal code for PSO/TSO. (Approximately nobody uses any

‎llvm/lib/Target/Sparc/SparcInstr64Bit.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,9 +157,11 @@ def : Pat<(and i64:$lhs, (not i64:$rhs)), (ANDNrr $lhs, $rhs)>;
157157
def : Pat<(or i64:$lhs, (not i64:$rhs)), (ORNrr $lhs, $rhs)>;
158158
def : Pat<(not (xor i64:$lhs, i64:$rhs)), (XNORrr $lhs, $rhs)>;
159159

160+
def : Pat<(addc i64:$lhs, i64:$rhs), (ADDCCrr $lhs, $rhs)>, Requires<[HasVIS3]>;
160161
def : Pat<(add i64:$lhs, i64:$rhs), (ADDrr $lhs, $rhs)>;
161162
def : Pat<(sub i64:$lhs, i64:$rhs), (SUBrr $lhs, $rhs)>;
162163

164+
def : Pat<(addc i64:$lhs, (i64 simm13:$rhs)), (ADDCCri $lhs, imm:$rhs)>, Requires<[HasVIS3]>;
163165
def : Pat<(add i64:$lhs, (i64 simm13:$rhs)), (ADDri $lhs, imm:$rhs)>;
164166
def : Pat<(sub i64:$lhs, (i64 simm13:$rhs)), (SUBri $lhs, imm:$rhs)>;
165167

‎llvm/lib/Target/Sparc/SparcInstrVIS.td‎

Lines changed: 61 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,10 @@ class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
4545
!strconcat(OpcStr, " $rs2, $rd")>;
4646

4747
// For VIS Instructions with only rd operand.
48-
let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
48+
let rs1 = 0, rs2 = 0 in
4949
class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
5050
: VISInstFormat<opfval,
51-
(outs RC:$rd), (ins RC:$f),
51+
(outs RC:$rd), (ins),
5252
!strconcat(OpcStr, " $rd")>;
5353

5454
// VIS 1 Instructions
@@ -259,14 +259,14 @@ def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
259259
(ins I64Regs:$rs2), "lzcnt $rs2, $rd">;
260260

261261
let rs1 = 0 in {
262-
def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
263-
(ins DFPRegs:$rs2), "movstosw $rs2, $rd">;
264-
def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
265-
(ins DFPRegs:$rs2), "movstouw $rs2, $rd">;
262+
def MOVSTOSW : VISInstFormat<0b100010011, (outs IntRegs:$rd),
263+
(ins FPRegs:$rs2), "movstosw $rs2, $rd">;
264+
def MOVSTOUW : VISInstFormat<0b100010001, (outs IntRegs:$rd),
265+
(ins FPRegs:$rs2), "movstouw $rs2, $rd">;
266266
def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd),
267267
(ins DFPRegs:$rs2), "movdtox $rs2, $rd">;
268-
def MOVWTOS : VISInstFormat<0b100011001, (outs DFPRegs:$rd),
269-
(ins I64Regs:$rs2), "movwtos $rs2, $rd">;
268+
def MOVWTOS : VISInstFormat<0b100011001, (outs FPRegs:$rd),
269+
(ins IntRegs:$rs2), "movwtos $rs2, $rd">;
270270
def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd),
271271
(ins I64Regs:$rs2), "movxtod $rs2, $rd">;
272272
}
@@ -277,3 +277,56 @@ def UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>;
277277
def XMULX : VISInst<0b100010101, "xmulx", I64Regs>;
278278
def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>;
279279
} // Predicates = [IsVIS3]
280+
281+
// FP immediate patterns.
282+
def fpimm0 : PatLeaf<(fpimm), [{return N->isExactlyValue(+0.0);}]>;
283+
def fpnegimm0 : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>;
284+
285+
// VIS instruction patterns.
286+
let Predicates = [HasVIS] in {
287+
// Zero immediate.
288+
def : Pat<(f64 fpimm0), (FZERO)>;
289+
def : Pat<(f32 fpimm0), (FZEROS)>;
290+
def : Pat<(f64 fpnegimm0), (FNEGD (FZERO))>;
291+
def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
292+
} // Predicates = [HasVIS]
293+
294+
// VIS3 instruction patterns.
295+
let Predicates = [HasVIS3] in {
296+
def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>;
297+
298+
def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>;
299+
// Signed "MULXHI".
300+
// Based on the formula presented in OSA2011 §7.140, but with bitops to select
301+
// the values to be added.
302+
def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)),
303+
(SUBrr (UMULXHI $lhs, $rhs),
304+
(ADDrr (ANDrr (SRAXri $lhs, 63), $rhs),
305+
(ANDrr (SRAXri $rhs, 63), $lhs)))>;
306+
307+
def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>;
308+
// 32-bit LZCNT.
309+
// The zero extension will leave us with 32 extra leading zeros,
310+
// so we need to compensate for it.
311+
def : Pat<(i32 (ctlz i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>;
312+
313+
def : Pat<(i32 (bitconvert f32:$src)), (MOVSTOUW $src)>;
314+
def : Pat<(i64 (zext (i32 (bitconvert f32:$src)))), (MOVSTOUW $src)>;
315+
def : Pat<(i64 (sext (i32 (bitconvert f32:$src)))), (MOVSTOSW $src)>;
316+
def : Pat<(f32 (bitconvert i32:$src)), (MOVWTOS $src)>;
317+
def : Pat<(i64 (bitconvert f64:$src)), (MOVDTOX $src)>;
318+
def : Pat<(f64 (bitconvert i64:$src)), (MOVXTOD $src)>;
319+
320+
// OP-then-neg FP operations.
321+
def : Pat<(f32 (fneg (fadd f32:$rs1, f32:$rs2))), (FNADDS $rs1, $rs2)>;
322+
def : Pat<(f64 (fneg (fadd f64:$rs1, f64:$rs2))), (FNADDD $rs1, $rs2)>;
323+
def : Pat<(f32 (fneg (fmul f32:$rs1, f32:$rs2))), (FNMULS $rs1, $rs2)>;
324+
def : Pat<(f32 (fmul (fneg f32:$rs1), f32:$rs2)), (FNMULS $rs1, $rs2)>;
325+
def : Pat<(f32 (fmul f32:$rs1, (fneg f32:$rs2))), (FNMULS $rs1, $rs2)>;
326+
def : Pat<(f64 (fneg (fmul f64:$rs1, f64:$rs2))), (FNMULD $rs1, $rs2)>;
327+
def : Pat<(f64 (fmul (fneg f64:$rs1), f64:$rs2)), (FNMULD $rs1, $rs2)>;
328+
def : Pat<(f64 (fmul f64:$rs1, (fneg f64:$rs2))), (FNMULD $rs1, $rs2)>;
329+
def : Pat<(f64 (fneg (fmul (fpextend f32:$rs1), (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;
330+
def : Pat<(f64 (fmul (fneg (fpextend f32:$rs1)), (fpextend f32:$rs2))), (FNSMULD $rs1, $rs2)>;
331+
def : Pat<(f64 (fmul (fpextend f32:$rs1), (fneg (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;
332+
} // Predicates = [HasVIS3]

‎llvm/test/CodeGen/SPARC/2011-01-11-CC.ll‎

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
; RUN: llc -mtriple=sparc %s -o - | FileCheck %s -check-prefix=V8
33
; RUN: llc -mtriple=sparc -mattr=v9 %s -o - | FileCheck %s -check-prefix=V9
44
; RUN: llc -mtriple=sparc64-unknown-linux %s -o - | FileCheck %s -check-prefix=SPARC64
5+
; RUN: llc -mtriple=sparc64-unknown-linux -mattr=vis3 %s -o - | FileCheck %s -check-prefix=SPARC64-VIS3
56

67
define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind {
78
; V8-LABEL: test_addx:
@@ -60,6 +61,15 @@ define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind {
6061
; SPARC64-NEXT: movgu %xcc, 1, %o3
6162
; SPARC64-NEXT: retl
6263
; SPARC64-NEXT: srl %o3, 0, %o0
64+
;
65+
; SPARC64-VIS3-LABEL: test_addx:
66+
; SPARC64-VIS3: ! %bb.0: ! %entry
67+
; SPARC64-VIS3-NEXT: mov %g0, %o3
68+
; SPARC64-VIS3-NEXT: add %o0, %o1, %o0
69+
; SPARC64-VIS3-NEXT: cmp %o0, %o2
70+
; SPARC64-VIS3-NEXT: movgu %xcc, 1, %o3
71+
; SPARC64-VIS3-NEXT: retl
72+
; SPARC64-VIS3-NEXT: srl %o3, 0, %o0
6373
entry:
6474
%0 = add i64 %a, %b
6575
%1 = icmp ugt i64 %0, %c
@@ -92,6 +102,13 @@ define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind {
92102
; SPARC64-NEXT: move %icc, %o1, %o2
93103
; SPARC64-NEXT: retl
94104
; SPARC64-NEXT: mov %o2, %o0
105+
;
106+
; SPARC64-VIS3-LABEL: test_select_int_icc:
107+
; SPARC64-VIS3: ! %bb.0: ! %entry
108+
; SPARC64-VIS3-NEXT: cmp %o0, 0
109+
; SPARC64-VIS3-NEXT: move %icc, %o1, %o2
110+
; SPARC64-VIS3-NEXT: retl
111+
; SPARC64-VIS3-NEXT: mov %o2, %o0
95112
entry:
96113
%0 = icmp eq i32 %a, 0
97114
%1 = select i1 %0, i32 %b, i32 %c
@@ -133,6 +150,13 @@ define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind {
133150
; SPARC64-NEXT: cmp %o0, 0
134151
; SPARC64-NEXT: retl
135152
; SPARC64-NEXT: fmovse %icc, %f3, %f0
153+
;
154+
; SPARC64-VIS3-LABEL: test_select_fp_icc:
155+
; SPARC64-VIS3: ! %bb.0: ! %entry
156+
; SPARC64-VIS3-NEXT: fmovs %f5, %f0
157+
; SPARC64-VIS3-NEXT: cmp %o0, 0
158+
; SPARC64-VIS3-NEXT: retl
159+
; SPARC64-VIS3-NEXT: fmovse %icc, %f3, %f0
136160
entry:
137161
%0 = icmp eq i32 %a, 0
138162
%1 = select i1 %0, float %f1, float %f2
@@ -182,6 +206,13 @@ define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind {
182206
; SPARC64-NEXT: cmp %o0, 0
183207
; SPARC64-NEXT: retl
184208
; SPARC64-NEXT: fmovde %icc, %f2, %f0
209+
;
210+
; SPARC64-VIS3-LABEL: test_select_dfp_icc:
211+
; SPARC64-VIS3: ! %bb.0: ! %entry
212+
; SPARC64-VIS3-NEXT: fmovd %f4, %f0
213+
; SPARC64-VIS3-NEXT: cmp %o0, 0
214+
; SPARC64-VIS3-NEXT: retl
215+
; SPARC64-VIS3-NEXT: fmovde %icc, %f2, %f0
185216
entry:
186217
%0 = icmp eq i32 %a, 0
187218
%1 = select i1 %0, double %f1, double %f2
@@ -229,6 +260,17 @@ define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind {
229260
; SPARC64-NEXT: fcmps %fcc0, %f1, %f0
230261
; SPARC64-NEXT: retl
231262
; SPARC64-NEXT: movne %fcc0, %o1, %o0
263+
;
264+
; SPARC64-VIS3-LABEL: test_select_int_fcc:
265+
; SPARC64-VIS3: ! %bb.0: ! %entry
266+
; SPARC64-VIS3-NEXT: sethi %h44(.LCPI4_0), %o0
267+
; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI4_0), %o0
268+
; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0
269+
; SPARC64-VIS3-NEXT: ld [%o0+%l44(.LCPI4_0)], %f0
270+
; SPARC64-VIS3-NEXT: mov %o2, %o0
271+
; SPARC64-VIS3-NEXT: fcmps %fcc0, %f1, %f0
272+
; SPARC64-VIS3-NEXT: retl
273+
; SPARC64-VIS3-NEXT: movne %fcc0, %o1, %o0
232274
entry:
233275
%0 = fcmp une float %f, 0.000000e+00
234276
%a.b = select i1 %0, i32 %a, i32 %b
@@ -284,6 +326,17 @@ define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind {
284326
; SPARC64-NEXT: fcmps %fcc0, %f1, %f2
285327
; SPARC64-NEXT: retl
286328
; SPARC64-NEXT: fmovsne %fcc0, %f3, %f0
329+
;
330+
; SPARC64-VIS3-LABEL: test_select_fp_fcc:
331+
; SPARC64-VIS3: ! %bb.0: ! %entry
332+
; SPARC64-VIS3-NEXT: sethi %h44(.LCPI5_0), %o0
333+
; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI5_0), %o0
334+
; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0
335+
; SPARC64-VIS3-NEXT: ld [%o0+%l44(.LCPI5_0)], %f2
336+
; SPARC64-VIS3-NEXT: fmovs %f5, %f0
337+
; SPARC64-VIS3-NEXT: fcmps %fcc0, %f1, %f2
338+
; SPARC64-VIS3-NEXT: retl
339+
; SPARC64-VIS3-NEXT: fmovsne %fcc0, %f3, %f0
287340
entry:
288341
%0 = fcmp une float %f, 0.000000e+00
289342
%1 = select i1 %0, float %f1, float %f2
@@ -352,6 +405,18 @@ define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind {
352405
; SPARC64-NEXT: fmovd %f4, %f0
353406
; SPARC64-NEXT: retl
354407
; SPARC64-NEXT: nop
408+
;
409+
; SPARC64-VIS3-LABEL: test_select_dfp_fcc:
410+
; SPARC64-VIS3: ! %bb.0: ! %entry
411+
; SPARC64-VIS3-NEXT: sethi %h44(.LCPI6_0), %o0
412+
; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI6_0), %o0
413+
; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0
414+
; SPARC64-VIS3-NEXT: ldd [%o0+%l44(.LCPI6_0)], %f6
415+
; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f0, %f6
416+
; SPARC64-VIS3-NEXT: fmovdne %fcc0, %f2, %f4
417+
; SPARC64-VIS3-NEXT: fmovd %f4, %f0
418+
; SPARC64-VIS3-NEXT: retl
419+
; SPARC64-VIS3-NEXT: nop
355420
entry:
356421
%0 = fcmp une double %f, 0.000000e+00
357422
%1 = select i1 %0, double %f1, double %f2
@@ -453,6 +518,31 @@ define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) nounwind {
453518
; SPARC64-NEXT: ! %bb.4: ! %exit.0
454519
; SPARC64-NEXT: retl
455520
; SPARC64-NEXT: mov %g0, %o0
521+
;
522+
; SPARC64-VIS3-LABEL: test_float_cc:
523+
; SPARC64-VIS3: ! %bb.0: ! %entry
524+
; SPARC64-VIS3-NEXT: sethi %h44(.LCPI7_0), %o0
525+
; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI7_0), %o0
526+
; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0
527+
; SPARC64-VIS3-NEXT: ldd [%o0+%l44(.LCPI7_0)], %f4
528+
; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f0, %f4
529+
; SPARC64-VIS3-NEXT: fbuge %fcc0, .LBB7_3
530+
; SPARC64-VIS3-NEXT: nop
531+
; SPARC64-VIS3-NEXT: ! %bb.1: ! %loop.2
532+
; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f2, %f4
533+
; SPARC64-VIS3-NEXT: fbule %fcc0, .LBB7_3
534+
; SPARC64-VIS3-NEXT: nop
535+
; SPARC64-VIS3-NEXT: ! %bb.2: ! %exit.1
536+
; SPARC64-VIS3-NEXT: retl
537+
; SPARC64-VIS3-NEXT: mov 1, %o0
538+
; SPARC64-VIS3-NEXT: .LBB7_3: ! %loop
539+
; SPARC64-VIS3-NEXT: ! =>This Inner Loop Header: Depth=1
540+
; SPARC64-VIS3-NEXT: cmp %o2, 10
541+
; SPARC64-VIS3-NEXT: be %icc, .LBB7_3
542+
; SPARC64-VIS3-NEXT: nop
543+
; SPARC64-VIS3-NEXT: ! %bb.4: ! %exit.0
544+
; SPARC64-VIS3-NEXT: retl
545+
; SPARC64-VIS3-NEXT: mov %g0, %o0
456546
entry:
457547
%0 = fcmp uge double %a, 0.000000e+00
458548
br i1 %0, label %loop, label %loop.2
@@ -558,6 +648,34 @@ define void @test_adde_sube(ptr %a, ptr %b, ptr %sum, ptr %diff) nounwind {
558648
; SPARC64-NEXT: stx %i0, [%i3]
559649
; SPARC64-NEXT: ret
560650
; SPARC64-NEXT: restore
651+
;
652+
; SPARC64-VIS3-LABEL: test_adde_sube:
653+
; SPARC64-VIS3: .register %g2, #scratch
654+
; SPARC64-VIS3-NEXT: ! %bb.0: ! %entry
655+
; SPARC64-VIS3-NEXT: save %sp, -128, %sp
656+
; SPARC64-VIS3-NEXT: ldx [%i0+8], %i4
657+
; SPARC64-VIS3-NEXT: ldx [%i0], %i5
658+
; SPARC64-VIS3-NEXT: ldx [%i1+8], %g2
659+
; SPARC64-VIS3-NEXT: ldx [%i1], %i1
660+
; SPARC64-VIS3-NEXT: addcc %i4, %g2, %g2
661+
; SPARC64-VIS3-NEXT: addxccc %i5, %i1, %i1
662+
; SPARC64-VIS3-NEXT: stx %i1, [%i2]
663+
; SPARC64-VIS3-NEXT: stx %g2, [%i2+8]
664+
; SPARC64-VIS3-NEXT: !APP
665+
; SPARC64-VIS3-NEXT: !NO_APP
666+
; SPARC64-VIS3-NEXT: ldx [%i0+8], %i1
667+
; SPARC64-VIS3-NEXT: mov %g0, %i2
668+
; SPARC64-VIS3-NEXT: ldx [%i0], %i0
669+
; SPARC64-VIS3-NEXT: cmp %i4, %i1
670+
; SPARC64-VIS3-NEXT: movcs %xcc, 1, %i2
671+
; SPARC64-VIS3-NEXT: srl %i2, 0, %i2
672+
; SPARC64-VIS3-NEXT: sub %i5, %i0, %i0
673+
; SPARC64-VIS3-NEXT: sub %i0, %i2, %i0
674+
; SPARC64-VIS3-NEXT: sub %i4, %i1, %i1
675+
; SPARC64-VIS3-NEXT: stx %i1, [%i3+8]
676+
; SPARC64-VIS3-NEXT: stx %i0, [%i3]
677+
; SPARC64-VIS3-NEXT: ret
678+
; SPARC64-VIS3-NEXT: restore
561679
entry:
562680
%0 = bitcast ptr %a to ptr
563681
%1 = bitcast ptr %b to ptr

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