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Commit 906cdbe

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VyacheslavLevytskyyVyacheslavLevytskyy
committed
improve validity of emitted code between passes
1 parent 72aefbb commit 906cdbe

14 files changed

+61
-29
lines changed

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1551,14 +1551,17 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
15511551
if (Reg.isValid())
15521552
return getSPIRVTypeForVReg(Reg);
15531553
// create a new type
1554-
auto MIB = BuildMI(MIRBuilder.getMBB(), MIRBuilder.getInsertPt(),
1555-
MIRBuilder.getDebugLoc(),
1556-
MIRBuilder.getTII().get(SPIRV::OpTypePointer))
1557-
.addDef(createTypeVReg(CurMF->getRegInfo()))
1558-
.addImm(static_cast<uint32_t>(SC))
1559-
.addUse(getSPIRVTypeID(BaseType));
1560-
DT.add(PointerElementType, AddressSpace, CurMF, getSPIRVTypeID(MIB));
1561-
return finishCreatingSPIRVType(LLVMTy, MIB);
1554+
return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
1555+
auto MIB = BuildMI(MIRBuilder.getMBB(), MIRBuilder.getInsertPt(),
1556+
MIRBuilder.getDebugLoc(),
1557+
MIRBuilder.getTII().get(SPIRV::OpTypePointer))
1558+
.addDef(createTypeVReg(CurMF->getRegInfo()))
1559+
.addImm(static_cast<uint32_t>(SC))
1560+
.addUse(getSPIRVTypeID(BaseType));
1561+
DT.add(PointerElementType, AddressSpace, CurMF, getSPIRVTypeID(MIB));
1562+
finishCreatingSPIRVType(LLVMTy, MIB);
1563+
return MIB;
1564+
});
15621565
}
15631566

15641567
SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2162,6 +2162,7 @@ bool SPIRVInstructionSelector::selectBuildVector(Register ResVReg,
21622162
report_fatal_error(
21632163
"There must be at least two constituent operands in a vector");
21642164

2165+
MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
21652166
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
21662167
TII.get(IsConst ? SPIRV::OpConstantComposite
21672168
: SPIRV::OpCompositeConstruct))
@@ -2195,6 +2196,7 @@ bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg,
21952196
report_fatal_error(
21962197
"There must be at least two constituent operands in a vector");
21972198

2199+
MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
21982200
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
21992201
TII.get(IsConst ? SPIRV::OpConstantComposite
22002202
: SPIRV::OpCompositeConstruct))
@@ -2701,7 +2703,7 @@ bool SPIRVInstructionSelector::wrapIntoSpecConstantOp(
27012703
continue;
27022704
}
27032705
// Create a new register for the wrapper
2704-
WrapReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
2706+
WrapReg = MRI->createVirtualRegister(GR.getRegClass(OpType));
27052707
GR.add(OpDefine, MF, WrapReg);
27062708
CompositeArgs.push_back(WrapReg);
27072709
// Decorate the wrapper register and generate a new instruction
@@ -2766,6 +2768,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
27662768
if (!wrapIntoSpecConstantOp(I, CompositeArgs))
27672769
return false;
27682770
}
2771+
MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
27692772
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
27702773
.addDef(ResVReg)
27712774
.addUse(GR.getSPIRVTypeID(ResType));
@@ -3388,7 +3391,10 @@ bool SPIRVInstructionSelector::selectPhi(Register ResVReg,
33883391
MIB.addUse(I.getOperand(i + 0).getReg());
33893392
MIB.addMBB(I.getOperand(i + 1).getMBB());
33903393
}
3391-
return MIB.constrainAllUses(TII, TRI, RBI);
3394+
bool Res = MIB.constrainAllUses(TII, TRI, RBI);
3395+
MIB->setDesc(TII.get(TargetOpcode::PHI));
3396+
MIB->removeOperand(1);
3397+
return Res;
33923398
}
33933399

33943400
bool SPIRVInstructionSelector::selectGlobalValue(

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1770,6 +1770,27 @@ static void addMBBNames(const Module &M, const SPIRVInstrInfo &TII,
17701770
}
17711771
}
17721772

1773+
// patching Instruction::PHI to SPIRV::OpPhi
1774+
static void patchPhis(const Module &M, SPIRVGlobalRegistry *GR,
1775+
const SPIRVInstrInfo &TII, MachineModuleInfo *MMI) {
1776+
for (auto F = M.begin(), E = M.end(); F != E; ++F) {
1777+
MachineFunction *MF = MMI->getMachineFunction(*F);
1778+
if (!MF)
1779+
continue;
1780+
for (auto &MBB : *MF) {
1781+
for (MachineInstr &MI : MBB) {
1782+
if (MI.getOpcode() != TargetOpcode::PHI)
1783+
continue;
1784+
MI.setDesc(TII.get(SPIRV::OpPhi));
1785+
Register ResTypeReg = GR->getSPIRVTypeID(
1786+
GR->getSPIRVTypeForVReg(MI.getOperand(0).getReg(), MF));
1787+
MI.insert(MI.operands_begin() + 1,
1788+
{MachineOperand::CreateReg(ResTypeReg, false)});
1789+
}
1790+
}
1791+
}
1792+
}
1793+
17731794
struct SPIRV::ModuleAnalysisInfo SPIRVModuleAnalysis::MAI;
17741795

17751796
void SPIRVModuleAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
@@ -1788,6 +1809,8 @@ bool SPIRVModuleAnalysis::runOnModule(Module &M) {
17881809

17891810
setBaseInfo(M);
17901811

1812+
patchPhis(M, GR, *TII, MMI);
1813+
17911814
addMBBNames(M, *TII, MMI, *ST, MAI);
17921815
addDecorations(M, *TII, MMI, *ST, MAI);
17931816

‎llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -466,8 +466,13 @@ void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
466466
for (auto &Op : MI.operands()) {
467467
if (!Op.isReg() || Op.isDef())
468468
continue;
469-
auto IdOpInfo = createNewIdReg(nullptr, Op.getReg(), MRI, *GR);
470-
MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg());
469+
Register OpReg = Op.getReg();
470+
SPIRVType *SpvType = GR->getSPIRVTypeForVReg(OpReg);
471+
auto IdOpInfo = createNewIdReg(SpvType, OpReg, MRI, *GR);
472+
MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(OpReg);
473+
const TargetRegisterClass *RC = GR->getRegClass(SpvType);
474+
if (RC != MRI.getRegClassOrNull(OpReg))
475+
MRI.setRegClass(OpReg, RC);
471476
Op.setReg(IdOpInfo.first);
472477
}
473478
}

‎llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp‎

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -130,13 +130,8 @@ FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
130130
return nullptr;
131131
}
132132

133-
// Disable passes that may break CFG.
133+
// A place to disable passes that may break CFG.
134134
void SPIRVPassConfig::addMachineSSAOptimization() {
135-
// Some standard passes that optimize machine instructions in SSA form uses
136-
// MI.isPHI() that doesn't account for OpPhi in SPIR-V and so are able to
137-
// break the CFG (e.g., MachineSink).
138-
disablePass(&MachineSinkingID);
139-
140135
TargetPassConfig::addMachineSSAOptimization();
141136
}
142137

‎llvm/test/CodeGen/SPIRV/branching/if-merging.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
1+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
22

33
;; NOTE: This does not check for structured control-flow operations.
44

‎llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
1+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
22

33
; CHECK-DAG: [[I32:%.+]] = OpTypeInt 32
44
; CHECK-DAG: [[BOOL:%.+]] = OpTypeBool

‎llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
1+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
22
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
33

44
; CHECK: OpFunction

‎llvm/test/CodeGen/SPIRV/half_no_extension.ll‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@
55
;; vstorea_half4_rtp( data, 0, f );
66
;; }
77

8-
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
8+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
9+
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
910

10-
; CHECK-SPIRV: OpCapability Float16Buffer
11-
; CHECK-SPIRV-NOT: OpCapability Float16
11+
; CHECK-DAG: OpCapability Float16Buffer
12+
; CHECK-DAG: OpCapability Float16
1213

1314
define spir_kernel void @test(<4 x float> addrspace(1)* %p, half addrspace(1)* %f) {
1415
entry:

‎llvm/test/CodeGen/SPIRV/keep-tracked-const.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; This test case ensures that cleaning of temporary constants doesn't purge tracked ones.
22

3-
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
3+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
44
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
55

66
; CHECK-SPIRV: %[[#Int:]] = OpTypeInt 32 0

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