Fixup

MacDue · MacDue · commit 909f6b0bd1c5 · 2025-10-03T09:14:04.000Z
Change-Id: I8085f63f150e9754952f256a86bed88bf4b40c95
diff --git a/llvm/test/CodeGen/AArch64/ssve-stack-hazard-remarks.ll b/llvm/test/CodeGen/AArch64/ssve-stack-hazard-remarks.ll
@@ -68,7 +68,7 @@ entry:
 }
 
 ; SVE calling conventions
-; Padding is placed predicate and fpr/zpr register spills, so only emit remarks when hazard padding is off.
+; Padding is placed between predicate and fpr/zpr register spills, so only emit remarks when hazard padding is off.
 ; Note: The -aarch64-enable-zpr-predicate-spills option is deprecated (and will be removed soon).
 
 define i32 @svecc_call(<4 x i16> %P0, ptr %P1, i32 %P2, <vscale x 16 x i8> %P3, i16 %P4) #2 {

Original file line number	Diff line number	Diff line change
`@@ -68,7 +68,7 @@ entry:`
`68`	`68`	`}`
`69`	`69`
`70`	`70`	`; SVE calling conventions`
`71`		`-; Padding is placed predicate and fpr/zpr register spills, so only emit remarks when hazard padding is off.`
	`71`	`+; Padding is placed between predicate and fpr/zpr register spills, so only emit remarks when hazard padding is off.`
`72`	`72`	`; Note: The -aarch64-enable-zpr-predicate-spills option is deprecated (and will be removed soon).`
`73`	`73`
`74`	`74`	`define i32 @svecc_call(<4 x i16> %P0, ptr %P1, i32 %P2, <vscale x 16 x i8> %P3, i16 %P4) #2 {`