[MCA][X86] Fix throughput of (V)PMOV extension/truncation 512-bit instructions

znver4 512-bit instructions are half rate of 128/256-bit variants (still 1uop though)

Confirmed with Agner/uops.info

Noticed while triaging #110308 and #117579

Author: RKSimon

llvm/lib/Target/X86/X86ScheduleZnver4.td

@@ -1652,7 +1652,7 @@ def : InstRW<[Zn4MOVS], (instregex
 
 def Zn4MOVSZ: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 4;
-  let ReleaseAtCycles = [4];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4MOVSZ], (instregex
@@ -1661,7 +1661,7 @@ def : InstRW<[Zn4MOVSZ], (instregex
 
 def Zn4MOVSrr: SchedWriteRes<[Zn4FPFMisc12]> {
   let Latency = 5;
-  let ReleaseAtCycles = [5];
+  let ReleaseAtCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4MOVSrr], (instregex