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ElvisWang123lukel97
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!fixup, Remove unneeded checks and check undelryingInstr is FPMO or not.
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-10
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2 files changed

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-10
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llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2290,8 +2290,7 @@ void VPReductionRecipe::execute(VPTransformState &State) {
22902290
"In-loop AnyOf reductions aren't currently supported");
22912291
// Propagate the fast-math flags carried by the underlying instruction.
22922292
IRBuilderBase::FastMathFlagGuard FMFGuard(State.Builder);
2293-
if (hasFastMathFlags())
2294-
State.Builder.setFastMathFlags(getFastMathFlags());
2293+
State.Builder.setFastMathFlags(getFastMathFlags());
22952294
State.setDebugLocFrom(getDebugLoc());
22962295
Value *NewVecOp = State.get(getVecOp());
22972296
if (VPValue *Cond = getCondOp()) {
@@ -2338,8 +2337,7 @@ void VPReductionEVLRecipe::execute(VPTransformState &State) {
23382337
// Propagate the fast-math flags carried by the underlying instruction.
23392338
IRBuilderBase::FastMathFlagGuard FMFGuard(Builder);
23402339
const RecurrenceDescriptor &RdxDesc = getRecurrenceDescriptor();
2341-
if (hasFastMathFlags())
2342-
Builder.setFastMathFlags(getFastMathFlags());
2340+
Builder.setFastMathFlags(getFastMathFlags());
23432341

23442342
RecurKind Kind = RdxDesc.getRecurrenceKind();
23452343
Value *Prev = State.get(getChainOp(), /*IsScalar*/ true);
@@ -2376,8 +2374,7 @@ InstructionCost VPReductionRecipe::computeCost(ElementCount VF,
23762374
Type *ElementTy = Ctx.Types.inferScalarType(this);
23772375
auto *VectorTy = cast<VectorType>(toVectorTy(ElementTy, VF));
23782376
unsigned Opcode = RdxDesc.getOpcode();
2379-
FastMathFlags FMFs =
2380-
hasFastMathFlags() ? getFastMathFlags() : FastMathFlags();
2377+
FastMathFlags FMFs = getFastMathFlags();
23812378

23822379
// TODO: Support any-of and in-loop reductions.
23832380
assert(
@@ -2413,7 +2410,8 @@ void VPReductionRecipe::print(raw_ostream &O, const Twine &Indent,
24132410
O << " = ";
24142411
getChainOp()->printAsOperand(O, SlotTracker);
24152412
O << " +";
2416-
printFlags(O);
2413+
if (isa<FPMathOperator>(getUnderlyingInstr()))
2414+
printFlags(O);
24172415
O << " reduce." << Instruction::getOpcodeName(RdxDesc.getOpcode()) << " (";
24182416
getVecOp()->printAsOperand(O, SlotTracker);
24192417
if (isConditional()) {
@@ -2434,7 +2432,8 @@ void VPReductionEVLRecipe::print(raw_ostream &O, const Twine &Indent,
24342432
O << " = ";
24352433
getChainOp()->printAsOperand(O, SlotTracker);
24362434
O << " +";
2437-
printFlags(O);
2435+
if (isa<FPMathOperator>(getUnderlyingInstr()))
2436+
printFlags(O);
24382437
O << " vp.reduce." << Instruction::getOpcodeName(RdxDesc.getOpcode()) << " (";
24392438
getVecOp()->printAsOperand(O, SlotTracker);
24402439
O << ", ";

llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ define i32 @reduction(ptr %a, i64 %n, i32 %start) {
101101
; IF-EVL-INLOOP-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
102102
; IF-EVL-INLOOP-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
103103
; IF-EVL-INLOOP-NEXT: WIDEN ir<[[LD1:%.+]]> = vp.load vp<[[PTR1]]>, vp<[[EVL]]>
104-
; IF-EVL-INLOOP-NEXT: REDUCE ir<[[ADD:%.+]]> = ir<[[RDX_PHI]]> + reassoc nsz arcp contract afn vp.reduce.add (ir<[[LD1]]>, vp<[[EVL]]>)
104+
; IF-EVL-INLOOP-NEXT: REDUCE ir<[[ADD:%.+]]> = ir<[[RDX_PHI]]> + vp.reduce.add (ir<[[LD1]]>, vp<[[EVL]]>)
105105
; IF-EVL-INLOOP-NEXT: SCALAR-CAST vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
106106
; IF-EVL-INLOOP-NEXT: EMIT vp<[[IV_NEXT]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
107107
; IF-EVL-INLOOP-NEXT: EMIT vp<[[IV_NEXT_EXIT:%.+]]> = add vp<[[IV]]>, vp<[[VFUF]]>
@@ -196,7 +196,7 @@ define i32 @reduction(ptr %a, i64 %n, i32 %start) {
196196
; NO-VP-INLOOP-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
197197
; NO-VP-INLOOP-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
198198
; NO-VP-INLOOP-NEXT: WIDEN ir<[[LD1:%.+]]> = load vp<[[PTR1]]>
199-
; NO-VP-INLOOP-NEXT: REDUCE ir<[[ADD:%.+]]> = ir<[[RDX_PHI]]> + reassoc nsz arcp contract afn reduce.add (ir<[[LD1]]>)
199+
; NO-VP-INLOOP-NEXT: REDUCE ir<[[ADD:%.+]]> = ir<[[RDX_PHI]]> + reduce.add (ir<[[LD1]]>)
200200
; NO-VP-INLOOP-NEXT: EMIT vp<[[IV_NEXT_EXIT:%.+]]> = add nuw vp<[[IV]]>, vp<[[VFUF]]>
201201
; NO-VP-INLOOP-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, vp<[[VTC]]>
202202
; NO-VP-INLOOP-NEXT: No successors

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