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[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to their SelectionDAG equivalents. NFC
This makes it easier to see if the SelectionDAG node has an equivalent without needing to check another file. Putting them in the same file helps associate them with the relevant ISA and any additional context that may be provided by comments. Naming is a little messy because we inconsistently use camel case and snake case in the SelectionDAG node names. Thus the GISel node names are named the same as the SelectionDAG node name with either GI or gi_ as a prefix.
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‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 0 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -33,70 +33,10 @@ def simm12Minus1NonzeroNonNeg1 : ImmLeaf<XLenVT, [{
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def ImmPlus1 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getSExtValue() + 1, SDLoc(N),
3535
N->getValuePtrVTpe(0));}]>;
36-
37-
def GINegImm : GICustomOperandRenderer<"renderNegImm">,
38-
GISDNodeXFormEquiv<NegImm>;
39-
40-
def GIImmSubFromXLen : GICustomOperandRenderer<"renderImmSubFromXLen">,
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GISDNodeXFormEquiv<ImmSubFromXLen>;
42-
def GIImmSubFrom32 : GICustomOperandRenderer<"renderImmSubFrom32">,
43-
GISDNodeXFormEquiv<ImmSubFrom32>;
44-
4536
def GIImmPlus1 :
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GICustomOperandRenderer<"renderImmPlus1">,
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GISDNodeXFormEquiv<ImmPlus1>;
4839

49-
def GIAddrRegImm :
50-
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
51-
GIComplexPatternEquiv<AddrRegImm>;
52-
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// FIXME: This is labelled as handling 's32', however the ComplexPattern it
54-
// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
55-
// parameter appears to be ignored so this pattern works for both, however we
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// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
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// here.
58-
def GIVLOp : GIComplexOperandMatcher<s32, "renderVLOp">,
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GIComplexPatternEquiv<VLOp>;
60-
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def gi_trailing_zero : GICustomOperandRenderer<"renderTrailingZeros">,
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GISDNodeXFormEquiv<TrailingZeros>;
63-
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// FIXME: This is labelled as handling 's32', however the ComplexPattern it
65-
// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
66-
// parameter appears to be ignored so this pattern works for both, however we
67-
// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
68-
// here.
69-
def GIShiftMaskXLen :
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GIComplexOperandMatcher<s32, "selectShiftMaskXLen">,
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GIComplexPatternEquiv<shiftMaskXLen>;
72-
def GIShiftMask32 :
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GIComplexOperandMatcher<s64, "selectShiftMask32">,
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GIComplexPatternEquiv<shiftMask32>;
75-
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def gi_sh1add_op : GIComplexOperandMatcher<s32, "selectSHXADDOp<1>">,
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GIComplexPatternEquiv<sh1add_op>;
78-
def gi_sh2add_op : GIComplexOperandMatcher<s32, "selectSHXADDOp<2>">,
79-
GIComplexPatternEquiv<sh2add_op>;
80-
def gi_sh3add_op : GIComplexOperandMatcher<s32, "selectSHXADDOp<3>">,
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GIComplexPatternEquiv<sh3add_op>;
82-
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def gi_sh1add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<1>">,
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GIComplexPatternEquiv<sh1add_uw_op>;
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def gi_sh2add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<2>">,
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GIComplexPatternEquiv<sh2add_uw_op>;
87-
def gi_sh3add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<3>">,
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GIComplexPatternEquiv<sh3add_uw_op>;
89-
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def gi_sexti32 : GIComplexOperandMatcher<s64, "selectSExtBits<32>">,
91-
GIComplexPatternEquiv<sexti32>;
92-
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def gi_zexti32 : GIComplexOperandMatcher<s64, "selectZExtBits<32>">,
94-
GIComplexPatternEquiv<zexti32>;
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def gi_zexti16 : GIComplexOperandMatcher<s32, "selectZExtBits<16>">,
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GIComplexPatternEquiv<zexti16>;
97-
def gi_zexti8 : GIComplexOperandMatcher<s32, "selectZExtBits<8>">,
98-
GIComplexPatternEquiv<zexti8>;
99-
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// Ptr type used in patterns with GlobalISelEmitter
10141
def PtrVT : PtrValueTypeByHwMode<XLenVT, 0>;
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -418,6 +418,8 @@ def NegImm : SDNodeXForm<imm, [{
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return CurDAG->getSignedTargetConstant(-N->getSExtValue(), SDLoc(N),
419419
N->getValueType(0));
420420
}]>;
421+
def GINegImm : GICustomOperandRenderer<"renderNegImm">,
422+
GISDNodeXFormEquiv<NegImm>;
421423

422424
// Return an immediate value minus 32.
423425
def ImmSub32 : SDNodeXForm<imm, [{
@@ -431,12 +433,16 @@ def ImmSubFromXLen : SDNodeXForm<imm, [{
431433
return CurDAG->getTargetConstant(XLen - N->getZExtValue(), SDLoc(N),
432434
N->getValueType(0));
433435
}]>;
436+
def GIImmSubFromXLen : GICustomOperandRenderer<"renderImmSubFromXLen">,
437+
GISDNodeXFormEquiv<ImmSubFromXLen>;
434438

435439
// Return an immediate subtracted from 32.
436440
def ImmSubFrom32 : SDNodeXForm<imm, [{
437441
return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
438442
N->getValueType(0));
439443
}]>;
444+
def GIImmSubFrom32 : GICustomOperandRenderer<"renderImmSubFrom32">,
445+
GISDNodeXFormEquiv<ImmSubFrom32>;
440446

441447
// Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
442448
// in which imm = imm0 + imm1 and both imm0 and imm1 are simm12. We make imm0
@@ -469,6 +475,8 @@ def TrailingZeros : SDNodeXForm<imm, [{
469475
return CurDAG->getTargetConstant(llvm::countr_zero(N->getZExtValue()),
470476
SDLoc(N), N->getValueType(0));
471477
}]>;
478+
def GITrailingZeros : GICustomOperandRenderer<"renderTrailingZeros">,
479+
GISDNodeXFormEquiv<TrailingZeros>;
472480

473481
def XLenSubTrailingOnes : SDNodeXForm<imm, [{
474482
uint64_t XLen = Subtarget->getXLen();
@@ -1267,13 +1275,26 @@ def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{
12671275
return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
12681276
}]>;
12691277
def sexti16 : ComplexPattern<XLenVT, 1, "selectSExtBits<16>">;
1278+
12701279
def sexti32 : ComplexPattern<i64, 1, "selectSExtBits<32>">;
1280+
def gi_sexti32 : GIComplexOperandMatcher<s64, "selectSExtBits<32>">,
1281+
GIComplexPatternEquiv<sexti32>;
1282+
12711283
def assertzexti32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
12721284
return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
12731285
}]>;
1286+
12741287
def zexti32 : ComplexPattern<i64, 1, "selectZExtBits<32>">;
1288+
def gi_zexti32 : GIComplexOperandMatcher<s64, "selectZExtBits<32>">,
1289+
GIComplexPatternEquiv<zexti32>;
1290+
12751291
def zexti16 : ComplexPattern<XLenVT, 1, "selectZExtBits<16>">;
1292+
def gi_zexti16 : GIComplexOperandMatcher<s32, "selectZExtBits<16>">,
1293+
GIComplexPatternEquiv<zexti16>;
1294+
12761295
def zexti8 : ComplexPattern<XLenVT, 1, "selectZExtBits<8>">;
1296+
def gi_zexti8 : GIComplexOperandMatcher<s32, "selectZExtBits<8>">,
1297+
GIComplexPatternEquiv<zexti8>;
12771298

12781299
def ext : PatFrags<(ops node:$A), [(sext node:$A), (zext node:$A)]>;
12791300

@@ -1357,6 +1378,17 @@ def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
13571378
// ISA only read the least significant 5 bits (RV32I) or 6 bits (RV64I).
13581379
def shiftMaskXLen : ComplexPattern<XLenVT, 1, "selectShiftMaskXLen", [], [], 0>;
13591380
def shiftMask32 : ComplexPattern<i64, 1, "selectShiftMask32", [], [], 0>;
1381+
// FIXME: This is labelled as handling 's32', however the ComplexPattern it
1382+
// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
1383+
// parameter appears to be ignored so this pattern works for both, however we
1384+
// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
1385+
// here.
1386+
def GIShiftMaskXLen :
1387+
GIComplexOperandMatcher<s32, "selectShiftMaskXLen">,
1388+
GIComplexPatternEquiv<shiftMaskXLen>;
1389+
def GIShiftMask32 :
1390+
GIComplexOperandMatcher<s64, "selectShiftMask32">,
1391+
GIComplexPatternEquiv<shiftMask32>;
13601392

13611393
class shiftop<SDPatternOperator operator>
13621394
: PatFrag<(ops node:$val, node:$count),
@@ -1382,6 +1414,9 @@ def PseudoAddTPRel : Pseudo<(outs GPR:$rd),
13821414

13831415
def : Pat<(FrameAddrRegImm (iPTR GPR:$rs1), simm12:$imm12),
13841416
(ADDI GPR:$rs1, simm12:$imm12)>;
1417+
def GIAddrRegImm :
1418+
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
1419+
GIComplexPatternEquiv<AddrRegImm>;
13851420

13861421
/// Stack probing
13871422

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,13 @@ def vec_rm : RISCVOp {
102102
// !X0 | X0 | VLMAX | Set vl to VLMAX
103103
// X0 | X0 | Value in vl | Keep current vl, just change vtype.
104104
def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;
105+
// FIXME: This is labelled as handling 's32', however the ComplexPattern it
106+
// refers to handles both i32 and i64 based on the HwMode. Currently this LLT
107+
// parameter appears to be ignored so this pattern works for both, however we
108+
// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
109+
// here.
110+
def GIVLOp : GIComplexOperandMatcher<s32, "renderVLOp">,
111+
GIComplexPatternEquiv<VLOp>;
105112

106113
def DecImm : SDNodeXForm<imm, [{
107114
return CurDAG->getSignedTargetConstant(N->getSExtValue() - 1, SDLoc(N),

‎llvm/lib/Target/RISCV/RISCVInstrInfoZb.td‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,10 +213,23 @@ def Shifted32OnesMask : IntImmLeaf<XLenVT, [{
213213
def sh1add_op : ComplexPattern<XLenVT, 1, "selectSHXADDOp<1>", [], [], 6>;
214214
def sh2add_op : ComplexPattern<XLenVT, 1, "selectSHXADDOp<2>", [], [], 6>;
215215
def sh3add_op : ComplexPattern<XLenVT, 1, "selectSHXADDOp<3>", [], [], 6>;
216+
def gi_sh1add_op : GIComplexOperandMatcher<s32, "selectSHXADDOp<1>">,
217+
GIComplexPatternEquiv<sh1add_op>;
218+
def gi_sh2add_op : GIComplexOperandMatcher<s32, "selectSHXADDOp<2>">,
219+
GIComplexPatternEquiv<sh2add_op>;
220+
def gi_sh3add_op : GIComplexOperandMatcher<s32, "selectSHXADDOp<3>">,
221+
GIComplexPatternEquiv<sh3add_op>;
222+
216223

217224
def sh1add_uw_op : ComplexPattern<XLenVT, 1, "selectSHXADD_UWOp<1>", [], [], 6>;
218225
def sh2add_uw_op : ComplexPattern<XLenVT, 1, "selectSHXADD_UWOp<2>", [], [], 6>;
219226
def sh3add_uw_op : ComplexPattern<XLenVT, 1, "selectSHXADD_UWOp<3>", [], [], 6>;
227+
def gi_sh1add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<1>">,
228+
GIComplexPatternEquiv<sh1add_uw_op>;
229+
def gi_sh2add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<2>">,
230+
GIComplexPatternEquiv<sh2add_uw_op>;
231+
def gi_sh3add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<3>">,
232+
GIComplexPatternEquiv<sh3add_uw_op>;
220233

221234
//===----------------------------------------------------------------------===//
222235
// Instruction class templates

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