Preserve exact flag for lshr

LU-JOHN · LU-JOHN · commit 9125754fb380 · 2025-07-07T08:16:50.000-05:00
Signed-off-by: John Lu &lt;John.Lu@amd.com&gt;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4328,7 +4328,8 @@ SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
     Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, LHSSL, TargetType, SplitLHS, One);
   }
 
-  SDValue NewShift = DAG.getNode(ISD::SRL, SL, TargetType, Hi, ShiftAmt);
+  SDValue NewShift =
+      DAG.getNode(ISD::SRL, SL, TargetType, Hi, ShiftAmt, N->getFlags());
 
   SDValue Vec;
   if (VT.isVector()) {

Original file line number	Diff line number	Diff line change
`@@ -4328,7 +4328,8 @@ SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,`
`4328`	`4328`	`Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, LHSSL, TargetType, SplitLHS, One);`
`4329`	`4329`	`}`
`4330`	`4330`
`4331`		`- SDValue NewShift = DAG.getNode(ISD::SRL, SL, TargetType, Hi, ShiftAmt);`
	`4331`	`+ SDValue NewShift =`
	`4332`	`+ DAG.getNode(ISD::SRL, SL, TargetType, Hi, ShiftAmt, N->getFlags());`
`4332`	`4333`
`4333`	`4334`	`SDValue Vec;`
`4334`	`4335`	`if (VT.isVector()) {`