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[AArch64][GlobalISel] Add basic scalar handling for i32 lround and lrint.
This covers the windows variants, where long == i32. We can treat them as legal and generate the expected fcvtas instruction. The lround/llround and lrint/llrint were rejigged to allow the common parts to legalize in the same manner.
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7 files changed

+65
-112
lines changed

7 files changed

+65
-112
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -432,11 +432,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
432432
.minScalar(0, s32)
433433
.scalarize(0);
434434

435-
getActionDefinitionsBuilder({G_INTRINSIC_LRINT, G_INTRINSIC_LLRINT})
436-
.legalFor({{s64, MinFPScalar}, {s64, s32}, {s64, s64}})
437-
.libcallFor({{s64, s128}})
438-
.minScalarOrElt(1, MinFPScalar);
439-
440435
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2,
441436
G_FLOG10, G_FTAN, G_FEXP, G_FEXP2, G_FEXP10,
442437
G_FACOS, G_FASIN, G_FATAN, G_FATAN2, G_FCOSH,
@@ -451,9 +446,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
451446
.minScalar(0, s32)
452447
.libcallFor({{s32, s32}, {s64, s32}, {s128, s32}});
453448

454-
getActionDefinitionsBuilder({G_LROUND, G_LLROUND})
449+
getActionDefinitionsBuilder({G_LROUND, G_INTRINSIC_LRINT})
450+
.legalFor({{s32, s32}, {s32, s64}, {s64, s32}, {s64, s64}})
451+
.legalFor(HasFP16, {{s32, s16}, {s64, s16}})
452+
.minScalar(1, s32)
453+
.libcallFor({{s64, s128}});
454+
getActionDefinitionsBuilder({G_LLROUND, G_INTRINSIC_LLRINT})
455455
.legalFor({{s64, s32}, {s64, s64}})
456-
.legalFor(HasFP16, {{s64, s16}})
456+
.legalFor(HasFP16, {{s32, s16}, {s64, s16}})
457457
.minScalar(0, s64)
458458
.minScalar(1, s32)
459459
.libcallFor({{s64, s128}});

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,7 @@
187187
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
188188
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
189189
# DEBUG-NEXT: G_INTRINSIC_LRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
190+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
190191
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
191192
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
192193
# DEBUG-NEXT: G_INTRINSIC_LLRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
@@ -698,7 +699,6 @@
698699
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
699700
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
700701
# DEBUG-NEXT: G_LLROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
701-
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
702702
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
703703
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
704704
# DEBUG-NEXT: G_BR (opcode {{[0-9]+}}): 0 type indices, 0 imm indices

‎llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
22
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3-
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4-
5-
; CHECK-GI: warning: Instruction selection used fallback path for testmhhs
6-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhws
7-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhxs
3+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
84

95
define i16 @testmhhs(half %x) {
106
; CHECK-LABEL: testmhhs:

‎llvm/test/CodeGen/AArch64/lrint-conv-win.ll‎

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
22
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3-
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4-
5-
; CHECK-GI: warning: Instruction selection used fallback path for testmsxs
6-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsws
7-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsxd
8-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmswd
3+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
94

105
define i64 @testmsxs(float %x) {
116
; CHECK-LABEL: testmsxs:

‎llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll‎

Lines changed: 18 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -3,60 +3,40 @@
33
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
define i16 @testmhhs(half %x) {
6-
; CHECK-SD-LABEL: testmhhs:
7-
; CHECK-SD: // %bb.0: // %entry
8-
; CHECK-SD-NEXT: fcvt s0, h0
9-
; CHECK-SD-NEXT: fcvtas w0, s0
10-
; CHECK-SD-NEXT: ret
11-
;
12-
; CHECK-GI-LABEL: testmhhs:
13-
; CHECK-GI: // %bb.0: // %entry
14-
; CHECK-GI-NEXT: fcvt s0, h0
15-
; CHECK-GI-NEXT: fcvtas x0, s0
16-
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
17-
; CHECK-GI-NEXT: ret
6+
; CHECK-LABEL: testmhhs:
7+
; CHECK: // %bb.0: // %entry
8+
; CHECK-NEXT: fcvt s0, h0
9+
; CHECK-NEXT: fcvtas w0, s0
10+
; CHECK-NEXT: ret
1811
entry:
1912
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
2013
%conv = trunc i32 %0 to i16
2114
ret i16 %conv
2215
}
2316

2417
define i32 @testmhws(half %x) {
25-
; CHECK-SD-LABEL: testmhws:
26-
; CHECK-SD: // %bb.0: // %entry
27-
; CHECK-SD-NEXT: fcvt s0, h0
28-
; CHECK-SD-NEXT: fcvtas w0, s0
29-
; CHECK-SD-NEXT: ret
30-
;
31-
; CHECK-GI-LABEL: testmhws:
32-
; CHECK-GI: // %bb.0: // %entry
33-
; CHECK-GI-NEXT: fcvt s0, h0
34-
; CHECK-GI-NEXT: fcvtas x0, s0
35-
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
36-
; CHECK-GI-NEXT: ret
18+
; CHECK-LABEL: testmhws:
19+
; CHECK: // %bb.0: // %entry
20+
; CHECK-NEXT: fcvt s0, h0
21+
; CHECK-NEXT: fcvtas w0, s0
22+
; CHECK-NEXT: ret
3723
entry:
3824
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
3925
ret i32 %0
4026
}
4127

4228
define i64 @testmhxs(half %x) {
43-
; CHECK-SD-LABEL: testmhxs:
44-
; CHECK-SD: // %bb.0: // %entry
45-
; CHECK-SD-NEXT: fcvt s0, h0
46-
; CHECK-SD-NEXT: fcvtas w8, s0
47-
; CHECK-SD-NEXT: sxtw x0, w8
48-
; CHECK-SD-NEXT: ret
49-
;
50-
; CHECK-GI-LABEL: testmhxs:
51-
; CHECK-GI: // %bb.0: // %entry
52-
; CHECK-GI-NEXT: fcvt s0, h0
53-
; CHECK-GI-NEXT: fcvtas x8, s0
54-
; CHECK-GI-NEXT: sxtw x0, w8
55-
; CHECK-GI-NEXT: ret
29+
; CHECK-LABEL: testmhxs:
30+
; CHECK: // %bb.0: // %entry
31+
; CHECK-NEXT: fcvt s0, h0
32+
; CHECK-NEXT: fcvtas w8, s0
33+
; CHECK-NEXT: sxtw x0, w8
34+
; CHECK-NEXT: ret
5635
entry:
5736
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
5837
%conv = sext i32 %0 to i64
5938
ret i64 %conv
6039
}
6140
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
62-
; CHECK: {{.*}}
41+
; CHECK-GI: {{.*}}
42+
; CHECK-SD: {{.*}}

‎llvm/test/CodeGen/AArch64/lround-conv-win.ll‎

Lines changed: 20 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -3,72 +3,49 @@
33
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
define i64 @testmsxs(float %x) {
6-
; CHECK-SD-LABEL: testmsxs:
7-
; CHECK-SD: // %bb.0: // %entry
8-
; CHECK-SD-NEXT: fcvtas w8, s0
9-
; CHECK-SD-NEXT: sxtw x0, w8
10-
; CHECK-SD-NEXT: ret
11-
;
12-
; CHECK-GI-LABEL: testmsxs:
13-
; CHECK-GI: // %bb.0: // %entry
14-
; CHECK-GI-NEXT: fcvtas x8, s0
15-
; CHECK-GI-NEXT: sxtw x0, w8
16-
; CHECK-GI-NEXT: ret
6+
; CHECK-LABEL: testmsxs:
7+
; CHECK: // %bb.0: // %entry
8+
; CHECK-NEXT: fcvtas w8, s0
9+
; CHECK-NEXT: sxtw x0, w8
10+
; CHECK-NEXT: ret
1711
entry:
1812
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
1913
%conv = sext i32 %0 to i64
2014
ret i64 %conv
2115
}
2216

2317
define i32 @testmsws(float %x) {
24-
; CHECK-SD-LABEL: testmsws:
25-
; CHECK-SD: // %bb.0: // %entry
26-
; CHECK-SD-NEXT: fcvtas w0, s0
27-
; CHECK-SD-NEXT: ret
28-
;
29-
; CHECK-GI-LABEL: testmsws:
30-
; CHECK-GI: // %bb.0: // %entry
31-
; CHECK-GI-NEXT: fcvtas x0, s0
32-
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
33-
; CHECK-GI-NEXT: ret
18+
; CHECK-LABEL: testmsws:
19+
; CHECK: // %bb.0: // %entry
20+
; CHECK-NEXT: fcvtas w0, s0
21+
; CHECK-NEXT: ret
3422
entry:
3523
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
3624
ret i32 %0
3725
}
3826

3927
define i64 @testmsxd(double %x) {
40-
; CHECK-SD-LABEL: testmsxd:
41-
; CHECK-SD: // %bb.0: // %entry
42-
; CHECK-SD-NEXT: fcvtas w8, d0
43-
; CHECK-SD-NEXT: sxtw x0, w8
44-
; CHECK-SD-NEXT: ret
45-
;
46-
; CHECK-GI-LABEL: testmsxd:
47-
; CHECK-GI: // %bb.0: // %entry
48-
; CHECK-GI-NEXT: fcvtas x8, d0
49-
; CHECK-GI-NEXT: sxtw x0, w8
50-
; CHECK-GI-NEXT: ret
28+
; CHECK-LABEL: testmsxd:
29+
; CHECK: // %bb.0: // %entry
30+
; CHECK-NEXT: fcvtas w8, d0
31+
; CHECK-NEXT: sxtw x0, w8
32+
; CHECK-NEXT: ret
5133
entry:
5234
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
5335
%conv = sext i32 %0 to i64
5436
ret i64 %conv
5537
}
5638

5739
define i32 @testmswd(double %x) {
58-
; CHECK-SD-LABEL: testmswd:
59-
; CHECK-SD: // %bb.0: // %entry
60-
; CHECK-SD-NEXT: fcvtas w0, d0
61-
; CHECK-SD-NEXT: ret
62-
;
63-
; CHECK-GI-LABEL: testmswd:
64-
; CHECK-GI: // %bb.0: // %entry
65-
; CHECK-GI-NEXT: fcvtas x0, d0
66-
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
67-
; CHECK-GI-NEXT: ret
40+
; CHECK-LABEL: testmswd:
41+
; CHECK: // %bb.0: // %entry
42+
; CHECK-NEXT: fcvtas w0, d0
43+
; CHECK-NEXT: ret
6844
entry:
6945
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
7046
ret i32 %0
7147
}
7248

7349
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
74-
; CHECK: {{.*}}
50+
; CHECK-GI: {{.*}}
51+
; CHECK-SD: {{.*}}

‎llvm/test/CodeGen/AArch64/vector-lrint.ll‎

Lines changed: 17 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=aarch64 -mattr=+neon |\
3-
; RUN: FileCheck %s --check-prefixes=CHECK-i32
3+
; RUN: FileCheck %s --check-prefixes=CHECK-i32,CHECK-i32-SD
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=aarch64 -mattr=+neon |\
55
; RUN: FileCheck %s --check-prefixes=CHECK-i64,CHECK-i64-SD
66
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=aarch64 -mattr=+neon \
@@ -10,19 +10,16 @@
1010
; RUN: -global-isel -global-isel-abort=2 2>&1 |\
1111
; RUN: FileCheck %s --check-prefixes=CHECK-i64,CHECK-i64-GI
1212

13-
; CHECK-i32-GI: warning: Instruction selection used fallback path for lrint_v1f16
14-
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f16
13+
; CHECK-i32-GI: warning: Instruction selection used fallback path for lrint_v2f16
1514
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f16
1615
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f16
1716
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f16
1817
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f16
19-
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v1f32
2018
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f32
2119
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f32
2220
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f32
2321
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f32
2422
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f32
25-
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v1f64
2623
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f64
2724
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f64
2825
; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f64
@@ -53,6 +50,9 @@
5350
; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4fp128
5451
; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8fp128
5552
; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16fp128
53+
;
54+
;
55+
;
5656

5757

5858
define <1 x iXLen> @lrint_v1f16(<1 x half> %x) nounwind {
@@ -759,11 +759,11 @@ define <32 x iXLen> @lrint_v32f16(<32 x half> %x) nounwind {
759759
declare <32 x iXLen> @llvm.lrint.v32iXLen.v32f16(<32 x half>)
760760

761761
define <1 x iXLen> @lrint_v1f32(<1 x float> %x) nounwind {
762-
; CHECK-i32-LABEL: lrint_v1f32:
763-
; CHECK-i32: // %bb.0:
764-
; CHECK-i32-NEXT: frintx v0.2s, v0.2s
765-
; CHECK-i32-NEXT: fcvtzs v0.2s, v0.2s
766-
; CHECK-i32-NEXT: ret
762+
; CHECK-i32-SD-LABEL: lrint_v1f32:
763+
; CHECK-i32-SD: // %bb.0:
764+
; CHECK-i32-SD-NEXT: frintx v0.2s, v0.2s
765+
; CHECK-i32-SD-NEXT: fcvtzs v0.2s, v0.2s
766+
; CHECK-i32-SD-NEXT: ret
767767
;
768768
; CHECK-i64-SD-LABEL: lrint_v1f32:
769769
; CHECK-i64-SD: // %bb.0:
@@ -773,6 +773,13 @@ define <1 x iXLen> @lrint_v1f32(<1 x float> %x) nounwind {
773773
; CHECK-i64-SD-NEXT: fmov d0, x8
774774
; CHECK-i64-SD-NEXT: ret
775775
;
776+
; CHECK-i32-GI-LABEL: lrint_v1f32:
777+
; CHECK-i32-GI: // %bb.0:
778+
; CHECK-i32-GI-NEXT: frintx s0, s0
779+
; CHECK-i32-GI-NEXT: fcvtzs w8, s0
780+
; CHECK-i32-GI-NEXT: fmov s0, w8
781+
; CHECK-i32-GI-NEXT: ret
782+
;
776783
; CHECK-i64-GI-LABEL: lrint_v1f32:
777784
; CHECK-i64-GI: // %bb.0:
778785
; CHECK-i64-GI-NEXT: frintx s0, s0
@@ -1791,5 +1798,3 @@ define <16 x iXLen> @lrint_v16fp128(<16 x fp128> %x) nounwind {
17911798
}
17921799
declare <16 x iXLen> @llvm.lrint.v16iXLen.v16fp128(<16 x fp128>)
17931800

1794-
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
1795-
; CHECK-i32-GI: {{.*}}

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