[AArch64][GlobalISel] Implicitly truncate APInt in matchExt combine.

The APInt using FirstRealElt + 1 is intended to match the next element, which
might overflow the size of MaskBits. This prevents a new assert in APInt from
triggering.

Author: davemgreen

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

@@ -90,7 +90,7 @@ std::optional<std::pair<bool, uint64_t>> getExtMask(ArrayRef<int> M,
 
   // Use APInt to handle overflow when calculating expected element.
   unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
-  APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
+  APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1, false, true);
 
   // The following shuffle indices must be the successive elements after the
   // first real element.

llvm/test/CodeGen/AArch64/arm64-ext.ll

@@ -122,3 +122,12 @@ define <4 x i16> @test_undef(<8 x i16> %tmp1, <8 x i16> %tmp2) {
   %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
   ret <4 x i16> %tmp3
 }
+
+define <2 x i64> @test_v2s64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_v2s64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ext v0.16b, v1.16b, v0.16b, #8
+; CHECK-NEXT:    ret
+  %s = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0>
+  ret <2 x i64> %s
+}