restore old non-autogenerated file

Author: rez5427

llvm/test/CodeGen/AArch64/arm64-vector-ext.ll

@@ -1,16 +1,15 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
+;CHECK: @func30
+;CHECK: movi.4h v1, #1
+;CHECK: and.8b v0, v0, v1
+;CHECK: ushll.4s  v0, v0, #0
+;CHECK: str  q0, [x0]
+;CHECK: ret
+
 %T0_30 = type <4 x i1>
 %T1_30 = type <4 x i32>
 define void @func30(%T0_30 %v0, ptr %p1) {
-; CHECK-LABEL: func30:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    movi.4h v1, #1
-; CHECK-NEXT:    and.8b v0, v0, v1
-; CHECK-NEXT:    ushll.4s v0, v0, #0
-; CHECK-NEXT:    str q0, [x0]
-; CHECK-NEXT:    ret
   %r = zext %T0_30 %v0 to %T1_30
   store %T1_30 %r, ptr %p1
   ret void
@@ -19,11 +18,9 @@ define void @func30(%T0_30 %v0, ptr %p1) {
 ; Extend from v1i1 was crashing things (PR20791). Make sure we do something
 ; sensible instead.
 define <1 x i32> @autogen_SD7918() {
-; CHECK-LABEL: autogen_SD7918:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    movi.2d v0, #0000000000000000
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT:    ret
+; CHECK-LABEL: autogen_SD7918
+; CHECK: movi.2d v0, #0000000000000000
+; CHECK-NEXT: ret
   %I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0
   %ZE = zext <1 x i1> %I29 to <1 x i32>
   ret <1 x i32> %ZE

llvm/test/CodeGen/AArch64/arm64-vshuffle.ll

@@ -1,11 +1,9 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
 
 define <8 x i1> @test1() {
 ; CHECK-LABEL: test1:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    movi.16b v0, #0
-; CHECK-NEXT:    ; kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
 entry:
   %Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
@@ -60,14 +58,9 @@ bb:
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 define <16 x i1> @test4(ptr %ptr, i32 %v) {
-; CHECK-LABEL: test4:
-; CHECK:       ; %bb.0: ; %bb
-; CHECK-NEXT:  Lloh0:
-; CHECK-NEXT:    adrp x8, lCPI3_0@PAGE
-; CHECK-NEXT:  Lloh1:
-; CHECK-NEXT:    ldr q0, [x8, lCPI3_0@PAGEOFF]
-; CHECK-NEXT:    ret
-; CHECK-NEXT:    .loh AdrpLdr Lloh0, Lloh1
+; CHECK-LABEL: _test4:
+; CHECK:         adrp    x[[REG3:[0-9]+]], lCPI3_0@PAGE
+; CHECK:         ldr     q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF]
 bb:
   %Shuff = shufflevector <16 x i1> zeroinitializer,
      <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,

llvm/test/CodeGen/ARM/readcyclecounter.ll

@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
 ; RUN: llc -mtriple=thumbv7-none-linux-gnueabi < %s | FileCheck %s
 ; RUN: llc -mtriple=armv7-none-linux-gnueabi -mattr=-perfmon < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON
@@ -18,8 +17,9 @@ define i64 @get_count() {
   ; As usual, exact registers only sort of matter but the cycle-count had better
   ; end up in r0 in the end.
 
+; CHECK: mrc p15, #0, r0, c9, c13, #0
+; CHECK: {{movs?}} r1, #0
 
+; CHECK-NO-PERFMON: {{movs?}} r0, #0
+; CHECK-NO-PERFMON: {{movs?}} r1, #0
 }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
-; CHECK-NO-PERFMON: {{.*}}

llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll

@@ -1,20 +1,14 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -mtriple=avr | FileCheck %s
 
 ; CHECK-LABEL: ret_struct_i8_i16_i8
 define { i8, i16, i8 } @ret_struct_i8_i16_i8() {
-; CHECK-LABEL: ret_struct_i8_i16_i8:
-; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    ldi r22, 64
-; CHECK-NEXT:    ldi r18, 0
-; CHECK-NEXT:    ldi r19, 4
-; CHECK-NEXT:    ldi r25, 11
-; CHECK-NEXT:    mov r23, r18
-; CHECK-NEXT:    mov r24, r19
-; CHECK-NEXT:    ret
 start:
   ; for some reason the i16 is loaded to r24:r25
   ; and then moved to r23:r24
+  ; CHECK: ldi r22, 64
+  ; CHECK-NEXT: r23,
+  ; CHECK-NEXT: r24,
+  ; CHECK-NEXT: r25, 11
   %0 = insertvalue {i8, i16, i8} undef, i8 64, 0
   %1 = insertvalue {i8, i16, i8} %0, i16 1024, 1
   %2 = insertvalue {i8, i16, i8} %1, i8 11, 2
@@ -23,16 +17,13 @@ start:
 
 ; CHECK-LABEL: ret_struct_i32_i16
 define { i32, i16 } @ret_struct_i32_i16() {
-; CHECK-LABEL: ret_struct_i32_i16:
-; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    ldi r18, 4
-; CHECK-NEXT:    ldi r19, 3
-; CHECK-NEXT:    ldi r20, 2
-; CHECK-NEXT:    ldi r21, 1
-; CHECK-NEXT:    ldi r22, 0
-; CHECK-NEXT:    ldi r23, 8
-; CHECK-NEXT:    ret
 start:
+  ; CHECK: ldi r18, 4
+  ; CHECK-NEXT: ldi r19, 3
+  ; CHECK-NEXT: ldi r20, 2
+  ; CHECK-NEXT: ldi r21, 1
+  ; CHECK-NEXT: ldi r22, 0
+  ; CHECK-NEXT: ldi r23, 8
   %0 = insertvalue { i32, i16 } undef, i32 16909060, 0
   %1 = insertvalue { i32, i16 } %0, i16 2048, 1
   ret { i32, i16} %1

llvm/test/CodeGen/BPF/BTF/filename.ll

@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -mtriple=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
 
@@ -9,22 +8,6 @@
 
 ; Function Attrs: norecurse nounwind readnone uwtable
 define dso_local i32 @test() local_unnamed_addr #0 !dbg !7 {
-; CHECK-LABEL: test:
-; CHECK:       .Ltest$local:
-; CHECK-NEXT:    .type .Ltest$local,@function
-; CHECK-NEXT:  .Lfunc_begin0:
-; CHECK-NEXT:    .file 1 "/home/yhs/ttmp" "/home/yhs/ttmp/t.c"
-; CHECK-NEXT:    .loc 1 1 0 # /home/yhs/ttmp/t.c:1:0
-; CHECK-NEXT:    .cfi_startproc
-; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    w0 = 0
-; CHECK-NEXT:  .Ltmp0:
-; CHECK-NEXT:    .loc 1 1 14 prologue_end # /home/yhs/ttmp/t.c:1:14
-; CHECK-NEXT:  .Ltmp1:
-; CHECK-NEXT:  .Ltmp2:
-; CHECK-NEXT:    exit
-; CHECK-NEXT:  .Ltmp3:
-; CHECK-NEXT:  .Ltmp4:
   ret i32 0, !dbg !11
 }
 

llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll

@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -mtriple=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s
 
@@ -9,24 +8,6 @@
 
 ; Function Attrs: nounwind readnone
 define dso_local i32 @f1(i32) local_unnamed_addr #0 !dbg !7 {
-; CHECK-LABEL: f1:
-; CHECK:       .Lf1$local:
-; CHECK-NEXT:    .type .Lf1$local,@function
-; CHECK-NEXT:  .Lfunc_begin0:
-; CHECK-NEXT:    .file 1 "/DNE" "t.c"
-; CHECK-NEXT:    .loc 1 1 0 # t.c:1:0
-; CHECK-NEXT:    .cfi_sections .debug_frame
-; CHECK-NEXT:    .cfi_startproc
-; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    #DEBUG_VALUE: f1:a1 <- $w1
-; CHECK-NEXT:    w0 = 0
-; CHECK-NEXT:  .Ltmp0:
-; CHECK-NEXT:    .loc 1 1 18 prologue_end # t.c:1:18
-; CHECK-NEXT:  .Ltmp1:
-; CHECK-NEXT:  .Ltmp2:
-; CHECK-NEXT:    exit
-; CHECK-NEXT:  .Ltmp3:
-; CHECK-NEXT:  .Ltmp4:
   call void @llvm.dbg.value(metadata i32 %0, metadata !12, metadata !DIExpression()), !dbg !13
   ret i32 0, !dbg !14
 }

llvm/test/CodeGen/BPF/fi_ri.ll

@@ -1,24 +1,19 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -mtriple=bpf -mcpu=v1 | FileCheck %s
 
 %struct.key_t = type { i32, [16 x i8] }
 
 ; Function Attrs: nounwind uwtable
 define i32 @test() #0 {
-; CHECK-LABEL: test:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    r6 = 0
-; CHECK-NEXT:    *(u32 *)(r10 - 8) = r6
-; CHECK-NEXT:    *(u64 *)(r10 - 16) = r6
-; CHECK-NEXT:    *(u64 *)(r10 - 24) = r6
-; CHECK-NEXT:    r1 = r10
-; CHECK-NEXT:    r1 += -20
-; CHECK-NEXT:    call test1
-; CHECK-NEXT:    r0 = r6
-; CHECK-NEXT:    exit
   %key = alloca %struct.key_t, align 4
+; CHECK: r1 = 0
+; CHECK: *(u32 *)(r10 - 8) = r1
+; CHECK: *(u64 *)(r10 - 16) = r1
+; CHECK: *(u64 *)(r10 - 24) = r1
   call void @llvm.memset.p0.i64(ptr align 4 %key, i8 0, i64 20, i1 false)
+; CHECK: r1 = r10
+; CHECK: r1 += -20
   %1 = getelementptr inbounds %struct.key_t, ptr %key, i64 0, i32 1, i64 0
+; CHECK: call test1
   call void @test1(ptr %1) #3
   ret i32 0
 }

llvm/test/CodeGen/BPF/inlineasm-wreg.ll

@@ -1,36 +1,18 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -mtriple=bpfel -mattr=+alu32 -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=bpfeb -mattr=+alu32 -verify-machineinstrs | FileCheck %s
 
 ; Test that %w works as input constraint
 ; CHECK-LABEL: test_inlineasm_w_input_constraint
 define dso_local i32 @test_inlineasm_w_input_constraint() {
-; CHECK-LABEL: test_inlineasm_w_input_constraint:
-; CHECK:       .Ltest_inlineasm_w_input_constraint$local:
-; CHECK-NEXT:    .type .Ltest_inlineasm_w_input_constraint$local,@function
-; CHECK-NEXT:    .cfi_startproc
-; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    w0 = 42
-; CHECK-NEXT:    #APP
-; CHECK-NEXT:    w0 = w0
-; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    exit
   tail call void asm sideeffect "w0 = $0", "w"(i32 42)
+; CHECK: w0 = w1
   ret i32 42
 }
 
 ; Test that %w works as output constraint
 ; CHECK-LABEL: test_inlineasm_w_output_constraint
 define dso_local i32 @test_inlineasm_w_output_constraint() {
-; CHECK-LABEL: test_inlineasm_w_output_constraint:
-; CHECK:       .Ltest_inlineasm_w_output_constraint$local:
-; CHECK-NEXT:    .type .Ltest_inlineasm_w_output_constraint$local,@function
-; CHECK-NEXT:    .cfi_startproc
-; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    #APP
-; CHECK-NEXT:    w0 = 42
-; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    exit
   %1 = tail call i32 asm sideeffect "$0 = $1", "=w,i"(i32 42)
+; CHECK: w0 = 42
   ret i32 %1
 }

llvm/test/CodeGen/BPF/rodata_1.ll

@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -mtriple=bpfel -mcpu=v1 -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=bpfeb -mcpu=v1 -verify-machineinstrs | FileCheck %s
 
@@ -32,24 +31,17 @@
 ; Function Attrs: nounwind
 define i32 @test() local_unnamed_addr #0 {
 ; CHECK-LABEL: test:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    r1 = g1 ll
-; CHECK-NEXT:    r0 = 0
-; CHECK-NEXT:    *(u8 *)(r1 + 1) = r0
-; CHECK-NEXT:    *(u8 *)(r1 + 0) = r0
-; CHECK-NEXT:    r2 = 1
-; CHECK-NEXT:    *(u8 *)(r1 + 2) = r2
-; CHECK-NEXT:    r1 = g2 ll
-; CHECK-NEXT:    *(u32 *)(r1 + 8) = r2
-; CHECK-NEXT:    *(u32 *)(r1 + 4) = r0
-; CHECK-NEXT:    *(u32 *)(r1 + 0) = r0
-; CHECK-NEXT:    *(u32 *)(r1 + 12) = r0
-; CHECK-NEXT:    *(u32 *)(r1 + 16) = r0
-; CHECK-NEXT:    exit
 
 entry:
     tail call void @llvm.memcpy.p0.p0.i64(ptr @g1, ptr @test.t1, i64 3, i1 false)
     tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 @g2, ptr align 4 @test.t2, i64 20, i1 false)
+; CHECK:  r1 = g1
+; CHECK:  r2 = 0
+; CHECK:  *(u8 *)(r1 + 1) = r2
+; CHECK:  r3 = 1
+; CHECK:  *(u8 *)(r1 + 2) = r3
+; CHECK:  r1 = g2
+; CHECK:  *(u32 *)(r1 + 8) = r3
     ret i32 0
 }
 ; CHECK: .section  .rodata,"a",@progbits

llvm/test/CodeGen/BPF/rodata_2.ll

@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -mtriple=bpfel -mcpu=v1 -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=bpfeb -mcpu=v1 -verify-machineinstrs | FileCheck %s
 
@@ -30,24 +29,21 @@
 ; Function Attrs: nounwind
 define i32 @test() local_unnamed_addr #0 {
 ; CHECK-LABEL: test:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    r1 = g ll
-; CHECK-NEXT:    r2 = 3
-; CHECK-NEXT:    *(u32 *)(r1 + 24) = r2
-; CHECK-NEXT:    r2 = 2
-; CHECK-NEXT:    *(u32 *)(r1 + 20) = r2
-; CHECK-NEXT:    r2 = 1
-; CHECK-NEXT:    *(u32 *)(r1 + 16) = r2
-; CHECK-NEXT:    r0 = 0
-; CHECK-NEXT:    *(u32 *)(r1 + 28) = r0
-; CHECK-NEXT:    *(u32 *)(r1 + 12) = r0
-; CHECK-NEXT:    *(u32 *)(r1 + 8) = r0
-; CHECK-NEXT:    *(u32 *)(r1 + 4) = r0
-; CHECK-NEXT:    *(u32 *)(r1 + 0) = r0
-; CHECK-NEXT:    exit
 
 entry:
     tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 @g, ptr align 4 @test.t2, i64 32, i1 false)
+; CHECK: r1 = g ll
+; CHECK: r2 = 3
+; CHECK: *(u32 *)(r1 + 24) = r2
+; CHECK: r2 = 2
+; CHECK: *(u32 *)(r1 + 20) = r2
+; CHECK: r2 = 1
+; CHECK: *(u32 *)(r1 + 16) = r2
+; CHECK: r2 = 0
+; CHECK: *(u32 *)(r1 + 28) = r2
+; CHECK: *(u32 *)(r1 + 8) = r2
+; CHECK: *(u32 *)(r1 + 4) = r2
+; CHECK: *(u32 *)(r1 + 0) = r2
       ret i32 0
 }
 ; CHECK: .section  .rodata.cst32,"aM",@progbits,32